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參數(shù)資料
| 型號： | TMS320UVC5409 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Fixed-Point Digital Signal Processor(定點DSP) |
| 中文描述： | 定點數(shù)字信號處理器（定點DSP）的 |
| 文件頁數(shù)： | 26/35頁 |
| 文件大小： | 443K |
| 代理商： | TMS320UVC5409 |
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TMS320UVC5409
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS102 – APRIL 1999
26
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
memory-mapped registers (continued)
Table 10. Peripheral Memory-Mapped Registers
NAME
ADDRESS
DESCRIPTION
TYPE
DRR20
20h
Data receive register 2
McBSP #0
DRR10
21h
Data receive register 1
McBSP #0
DXR20
22h
Data transmit register 2
McBSP #0
DXR10
23h
Data transmit register 1
McBSP #0
TIM
24h
Timer register
Timer
PRD
25h
Timer period counter
Timer
TCR
26h
Timer control register
Timer
–
27h
Reserved
SWWSR
28h
Software wait-state register
External Bus
BSCR
29h
Bank-switching control register
External Bus
–
2Ah
Reserved
SWCR
2Bh
Software wait-state control register
External Bus
HPIC
2Ch
HPI control register
HPI
–
2Dh–2Fh
Reserved
DRR22
30h
Data receive register 2
McBSP #2
DRR12
31h
Data receive register 1
McBSP #2
DXR22
32h
Data transmit register 2
McBSP #2
DXR12
33h
Data transmit register 2
McBSP #2
SPSA2
34h
McBSP2 subbank address register
McBSP #2
SPSD2
35h
McBSP2 subbank data register
McBSP #2
–
36–37h
Reserved
SPSA0
38h
McBSP0 subbank address register
McBSP #0
SPCD0
39h
McBSP0 subbank data register
McBSP #0
–
3Ah–3Bh
Reserved
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GPIOCR
3C
General-purpose I/O pins control register
GPIO
DRR21
40h
Data receive register 1
McBSP #1
DRR11
41h
Data receive register 2
McBSP #1
DXR21
42h
Data transmit register 1
McBSP #1
DXR11
43h
Data transmit register 2
McBSP #1
–
44h–47h
Reserved
SPSA1
48h
McBSP1 subbank address register
McBSP #1
SPCD1
49h
McBSP1 subbank data register
McBSP #1
–
4Ah–53h
Reserved
DMPREC
54h
DMA channel priority and enable control register
DMA
DMSA
55h
DMA subbank address register
DMA
DMSDI
56h
DMA subbank data register with autoincrement
DMA
DMSDN
57h
DMA subbank data registrer
DMA
ááááááááááááááááááááááááááááááá
–
CLKMD
59h–5Fh
58h
Reserved
Clock mode register
PLL
A
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