參數(shù)資料
型號： TMS320LC57S
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Digital Signal Processors(35/50ns指令周期，并行邏輯單元，可編程PLL，全雙工同步串行口的DSP)
中文描述： 數(shù)字信號處理器（35/50ns指令周期，并行邏輯單元，可編程鎖相環(huán)，全雙工同步串行口的數(shù)字信號處理器）
文件頁數(shù)： 67/87頁
文件大?。?/td> 1864K
代理商： TMS320LC57S
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
67
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
EXTERNAL DMA
switching characteristics over recommended operating conditions [H = 0.5t
c(CO)
] (see Note 7)
(see Figure 21)
PARAMETER
’320C5x-40
’320C5x-57
’320LC5x-40
’320LC5x-50
MIN
’320C5x-80
’320LC5x-80
’320C5x-100
UNIT
MAX
MIN
MAX
MIN
MAX
td(HOL-HAL)
td(HOH-HAH)
th(AZ-HAL)
ten(HAH-Ad)
td(XBL-IQL)
td(XBH-IQH)
td(XSL-RDV)
th(XSH-RD)
ten(IQL-RDd)
th(XRL-DZ)
th(IQH-DZ)
ten(D-XRH)
HOLD is not acknowledged until current external access request is complete.
This parameter includes all memory control lines.
§Values derived from characterization data and not tested
This parameter refers to the delay between the time the condition (IAQ = 0 and XR/W = 1) is satisfied and the time that the ’C5x data lines become
valid.
NOTE 7: X preceding a name refers to external drive of the signal.
Delay time, HOLD low to HOLDA low
4H
4H
4H
ns
Delay time, HOLD high before HOLDA high
Address high-impedance before HOLDA low
2H
2H
2H
ns
H – 15§
H – 5§
4H§
2H§
H – 10§
H – 4§
4H§
2H§
H – 8§
H – 3§
4H§
2H§
ns
Enable time, HOLDA high to address driven
ns
Delay time, XBR low to IAQ low
6H§
4H§
6H§
4H§
6H§
4H§
ns
Delay time, XBR high to IAQ high
ns
Delay time, read data valid after XSTRB low
40
29
25
ns
Hold time, read data valid after XSTRB high
Enable time, IAQ low to read data driven
0
0
0
ns
0§
0§
2H§
15§
H§
4§
0§
0§
2H§
10§
H§
3§
0§
0§
2H§
ns
Hold time, XR/W low to data high impedance
8
ns
Hold time, IAQ high to data high impedance
H§
2§
ns
Enable time, data from XR/W going high
ns
timing requirements over recommended ranges of supply voltage and operating ambient-air
temperature (see Note 7) (see Figure 21)
’320C5x-40
’320C5x-57
’320LC5x-40
’320LC5x-50
MIN
0§
0§
’320C5x-80
’320LC5x-80
’320C5x-100
UNIT
MAX
MIN
0§
0§
MAX
MIN
0§
0§
MAX
td(HAL-XBL)
td(IQL-XSL)
tsu(AV-XSL)
tsu(DV-XSL)
th(XSL-D)
th(XSL-WA)
tw(XSL)
tw(XSH)
tsu(RW-XSL)
th(XSH-RA)
§Values derived from characterization data and not tested
#XBR, XR/W, and XSTRB lines must be pulled up with a 10-k
resistor to be certain that they are in an inactive high state during the transition
period between the ’C5x driving them and the external circuit driving them.
NOTE 7: X preceding a name refers to external drive of the signal.
Delay time, HOLDA low to XBR low#
Delay time, IAQ low to XSTRB low#
ns
ns
Setup time, Xaddress valid before XSTRB low
15
12
10
ns
Setup time, Xdata valid before XSTRB low
15
12
10
ns
Hold time, Xdata hold after XSTRB low
15
12
10
ns
Hold time, write Xaddress hold after XSTRB low
15
12
10
ns
Pulse duration, XSTRB low
45
40
35
ns
Pulse duration, XSTRB high
45
40
35
ns
Setup time, R/W valid before XSTRB low
20
20
18
ns
Hold time, read Xaddress after XSTRB high
0
0
0
ns
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TMS320LF2401AVFS 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 16-Bit Fixed-Pt DSP with Flash RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT
TMS320LF2402APGA 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 16-Bit Fixed-Pt DSP with Flash RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT
TMS320LF2402APGAR 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 18-Bit Univ Bus Drv With 3-State Outputs RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT
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