- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385940 > TMS320LC57S (Texas Instruments, Inc.) Digital Signal Processors(35/50ns指令周期，并行邏輯單元，可編程PLL，全雙工同步串行口的DSP) PDF資料下載
參數(shù)資料
| 型號： | TMS320LC57S |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Digital Signal Processors(35/50ns指令周期，并行邏輯單元，可編程PLL，全雙工同步串行口的DSP) |
| 中文描述： | 數(shù)字信號處理器（35/50ns指令周期，并行邏輯單元，可編程鎖相環(huán)，全雙工同步串行口的數(shù)字信號處理器） |
| 文件頁數(shù)： | 31/87頁 |
| 文件大小： | 1864K |
| 代理商： | TMS320LC57S |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁當前第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
31
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
host port interface (continued)
The HPI has two modes of operation, shared-access mode (SAM) and host-only mode (HOM). In SAM, the
normal mode of operation, both the ’C57S/’LC57 and the host can access HPI memory. In this mode,
asynchronous host accesses are resynchronized internally and, in case of conflict, the host has access priority
and the ’C57S/’LC57S waits one cycle. Host and CPU accesses to the HPI memory can be resychronized
through polling of a command word or through interrupts to prevent stalling the CPU for one cycle. The HOM
capability allows the host to access HPI memory while the ’C57S/’LC57 is in IDLE2 mode (all internal clocks
stopped) or in reset mode. The external ’C57S/’LC57S clock even can be stopped. The host can, therefore,
access the HPI RAM while the ’C57S/’LC57 is in its optimum configuration in terms of power consumption.
The HPI control register has two data strobes, HDS1 and HDS2, a read/write strobe HR/W, and an address
strobe HAS, to enable a glueless interface to a variety of industry-standard host devices. The HPI is easily
interfaced to hosts with multiplexed address/data bus, separate address and data buses, one data strobe, and
a read/write strobe, or two separate strobes for read and write. An HPI-ready pin, HRDY, is provided to specify
wait states for hosts that support an asynchronous input. When the ’C57S/’LC57 operating frequency is
variable, or when the host is capable of accessing at a faster rate than the maximum shared-access mode
access rate, the HRDY pin provides a convenient way to adjust the host access rate automatically (no software
handshake needed) to a change in the ’C57S/’LC57 clock rate or an HPI-mode switch.
The HPI supports high-speed back-to-back accesses. In the shared-access mode, the HPI can handle one byte
every five ’C57S/’LC57 periods (that is, 64 Mb/s with a 40-MHz ’C57S/’LC57). The HPI is designed so that the
host can take advantage of this high bandwidth and run at frequencies up to (f
of host cycles for an external access and f is the ’C57S/’LC57 frequency. In host-only mode, the HPI supports
even higher speed back-to-back host accesses: 1 byte every 50 ns (that is, 160 Mb/s) independently of the
’C57S/’LC57 clock rate.
n)
÷
5, where n is the number
serial ports
The ’C5x provides high-speed full-duplex serial ports that allow direct interface to other ’C5x devices, codecs,
and other devices in a system. There is a general-purpose serial port, a time-division-multiplexed (TDM) serial
port, and an auto-buffered serial port (BSP).
The general-purpose serial port uses two memory-mapped registers for data transfer: the data-transmit register
(DXR) and the data-receive register (DRR). Both registers can be accessed in the same manner as any other
memory location. The transmit and receive sections of the serial port each have associated clocks,
frame-synchronization pulses, and serial shift registers, and serial data can be transferred either in bytes or in
16-bit words. Serial port receive and transmit operations can generate their own maskable transmit and receive
interrupts (XINT and RINT), allowing serial port transfers to be managed by way of software. The ’C5x serial
ports are double-buffered and fully static.
The TDM port allows the device to communicate through time-division multiplexing with up to seven other ’C5x
devices with TDM ports. Time-division multiplexing is the division of time intervals into a number of subintervals
with each subinterval representing a prespecified communications channel. The TDM port serially transmits
16-bit words on a single data line (TDAT) and destination addresses on a single address line (TADD). Each
device can transmit data on a single channel and receive data from one or more of the eight channels providing
a simple and efficient interface for multiprocessing applications. A frame synchronization pulse occurs once
every 128 clock cycles corresponding to transmission of one 16-bit word on each of the eight channels. Like
the general-purpose serial port, the TDM port is double-buffered on both input and output data. The TDM port
also can be configured in software to operate as a general-purpose serial port as described above. Both types
of ports are capable of operating at up to one-fourth the machine cycle rate (CLKOUT1).
The buffered serial port (BSP) consists of a full-duplex double-buffered serial port interface (SPI) and an
auto-buffering unit (ABU). The SPI block of the BSP is an enhanced version of the general-purpose serial port.
The auto-buffering unit allows the SPI to read/write directly to ’C5x internal memory using a dedicated bus
independently of the CPU. This results in minimum overhead for SPI transactions and faster data rates.
相關PDF資料 |
PDF描述 |
|---|---|
| TMS320UVC5409 | Fixed-Point Digital Signal Processor(定點DSP) |
| TMS320VC203 | Digital Signal Processors(50ns指令周期， 空閑狀態(tài)CPU全關斷，先進的外圍，多種PLL可選) |
| TN-83 | MICROWAVE NOISE TUBES & NOISE SOURCES |
| TN-101 | CONNECTOR ACCESSORY |
| TN-102 | MICROWAVE NOISE TUBES & NOISE SOURCES |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TMS320LF2401AVFA | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Controller RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
| TMS320LF2401AVFS | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 16-Bit Fixed-Pt DSP with Flash RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
| TMS320LF2402APGA | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 16-Bit Fixed-Pt DSP with Flash RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
| TMS320LF2402APGAR | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 18-Bit Univ Bus Drv With 3-State Outputs RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
| TMS320LF2402APGS | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 16-Bit Fixed-Pt DSP with Flash RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
發(fā)布緊急采購，3分鐘左右您將得到回復。