- 您現(xiàn)在的位置：買賣IC網 > PDF目錄385940 > TMS320LC57S (Texas Instruments, Inc.) Digital Signal Processors(35/50ns指令周期，并行邏輯單元，可編程PLL，全雙工同步串行口的DSP) PDF資料下載
參數(shù)資料
| 型號： | TMS320LC57S |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Digital Signal Processors(35/50ns指令周期，并行邏輯單元，可編程PLL，全雙工同步串行口的DSP) |
| 中文描述： | 數(shù)字信號處理器（35/50ns指令周期，并行邏輯單元，可編程鎖相環(huán)，全雙工同步串行口的數(shù)字信號處理器） |
| 文件頁數(shù)： | 33/87頁 |
| 文件大?。?/td> | 1864K |
| 代理商： | TMS320LC57S |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁當前第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
33
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
IEEE 1149.1 boundary scan interface
The IEEE 1149.1 boundary-scan interface is used for emulation and test purposes. The IEEE 1149.1 scanning
logic provides the boundary-scan path to and from the interfacing devices. Also, it can be used to test pin-to-pin
continuity as well as to perform operational tests on those peripheral devices that surround the ’C5x. On ’C5x
devices which do not provide boundary-scan capability, the IEEE 1149.1 interface is used for emulation
purposes only. It is interfaced to other internal scanning logic circuitry, which has access to all of the on-chip
resources. Thus, the ’C5x can perform on-board emulation by means of IEEE 1149.1 serial pins and the
emulation-dedicated pins (see IEEE Standard 1149.1 for more details). Table 5 shows IEEE 1149.1 and
boundary-scan functions supported by the ’C5x family of devices.
Table 5. IEEE 1149.1 Interface/Boundary Scan/On-Chip Analysis Block Configurations
on the ’C5x/’LC5x Device Family
DEVICE TYPE
IEEE 1149.1 INTERFACE
BOUNDARY-SCAN CAPABILITY
ON-CHIP ANALYSIS BLOCK
’C50/’LC50
Yes
Yes
Full
’C51/’LC51
Yes
Yes
Full
’C52/’LC52
Yes
No
Full
’C53/’LC53
Yes
Yes
Full
’C53S/’LC53S
Yes
No
Reduced
’LC56
Yes
No
Full
’C57S
Yes
Yes
Full
’LC57
Yes
No
Full
on-chip analysis block
The on-chip analysis block, in conjunction with the ’C5x EVM, provides the capability to perform a variety of
debugging and performance evaluation functions in a target system. The full analysis block provides capability
for message passing by a combination of monitor mode and scan, flexible breakpoint setup based on events,
counting of events, and a PC discontinuity trace buffer. Breakpoints can be triggered based on the following
events: program fetches/reads/writes, EMU0/1 pin activity (used in multiprocessing), data reads/writes, CPU
events (calls, returns, interrupts/traps, branches, pipeline clock), and event-counter overflow. The event counter
is a 16-bit counter which can be used for performance analysis. The event counter can be incremented based
on the occurrence of the following events: CPU clocks (performance monitoring), pipeline advances, instruction
fetches (used to count instructions for an algorithm), branches, calls, returns, interrupts/traps, program
reads/writes, or data reads/writes. The PC discontinuity-trace buffer provides a method to monitor program
counter flow.
These analysis functions are available on all ’C5x devices except the ’C53S and ’LC53S which have a reduced
analysis block (see Table 5). The reduced analysis block provides capability for message passing and
breakpoints based on program fetches/reads/writes and EMU0/1 pin activity.
multiprocessing
The flexibility of the ’C5x allows configurations to satisfy a wide range of system requirements; the device can
be used in a variety of system configurations, including, but not limited to, the following:
A standalone processor
A multiprocessor with devices in parallel
A slave/host multiprocessor with global-memory space
A peripheral processor interfaced via processor-controlled signals to another device
相關PDF資料 |
PDF描述 |
|---|---|
| TMS320UVC5409 | Fixed-Point Digital Signal Processor(定點DSP) |
| TMS320VC203 | Digital Signal Processors(50ns指令周期， 空閑狀態(tài)CPU全關斷，先進的外圍，多種PLL可選) |
| TN-83 | MICROWAVE NOISE TUBES & NOISE SOURCES |
| TN-101 | CONNECTOR ACCESSORY |
| TN-102 | MICROWAVE NOISE TUBES & NOISE SOURCES |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TMS320LF2401AVFA | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Controller RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
| TMS320LF2401AVFS | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 16-Bit Fixed-Pt DSP with Flash RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
| TMS320LF2402APGA | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 16-Bit Fixed-Pt DSP with Flash RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
| TMS320LF2402APGAR | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 18-Bit Univ Bus Drv With 3-State Outputs RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
| TMS320LF2402APGS | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 16-Bit Fixed-Pt DSP with Flash RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
發(fā)布緊急采購，3分鐘左右您將得到回復。