參數(shù)資料
型號： TMS320F28044ZGMS
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Digital Signal Processor
中文描述： 數(shù)字信號處理器
文件頁數(shù)： 93/107頁
文件大?。?/td> 784K
代理商： TMS320F28044ZGMS
www.ti.com
SPRS357B–AUGUST 2006–REVISED MAY 2007
Table 6-27. SPI Master Mode External Timing (Clock Phase = 1)
(1)(2)(3)(4)(5)
NO.
SPI WHEN (SPIBRR + 1) IS EVEN
OR SPIBRR = 0 OR 2
MIN
4t
c(LCO)
0.5t
c(SPC)M
-10
SPI WHEN (SPIBRR + 1) IS ODD
AND SPIBRR > 3
MIN
5t
c(LCO)
0.5t
c(SPC)M
- 0.5t
c (LCO)
-10
UNIT
MAX
MAX
1
2
t
c(SPC)M
t
w(SPCH)M
Cycle time, SPICLK
Pulse duration, SPICLK high (clock
polarity = 0)
Pulse duration, SPICLK low (clock
polarity = 1)
Pulse duration, SPICLK low (clock
polarity = 0)
Pulse duration, SPICLK high (clock
polarity = 1)
Setup time, SPISIMO data valid
before SPICLK high (clock polarity
= 0)
Setup time, SPISIMO data valid
before SPICLK low (clock polarity =
1)
Valid time, SPISIMO data valid after
SPICLK high (clock polarity = 0)
Valid time, SPISIMO data valid after
SPICLK low (clock polarity = 1)
Setup time, SPISOMI before
SPICLK high (clock polarity = 0)
Setup time, SPISOMI before
SPICLK low (clock polarity = 1)
Valid time, SPISOMI data valid after
SPICLK high (clock polarity = 0)
Valid time, SPISOMI data valid after
SPICLK low (clock polarity = 1)
128t
c(LCO)
0.5t
c(SPC)M
ns
ns
0.5t
t
w(SPCL))M
0.5t
c(SPC)M
-10
0.5t
c(SPC)M
0.5t
c(SPC)M
- 0.5t
c (LCO)
-10
0.5t
ns
3
t
w(SPCL)M
0.5t
c(SPC)M
-10
0.5t
c(SPC)M
0.5t
c(SPC)M
+ 0.5t
c(LCO)
- 10
0.5t
ns
t
w(SPCH)M
0.5t
c(SPC)M
-10
0.5t
c(SPC)M
0.5
tc(SPC)M
+ 0.5t
c(LCO)
-10
0.5t
ns
6
t
su(SIMO-SPCH)M
0.5t
c(SPC)M
-10
0.5t
c(SPC)M
- 10
ns
t
su(SIMO-SPCL)M
0.5t
c(SPC)M
-10
0.5t
c(SPC)M
- 10
ns
7
t
v(SPCH-SIMO)M
0.5t
c(SPC)M
-10
0.5t
c(SPC)M
- 10
ns
t
v(SPCL-SIMO)M
0.5t
c(SPC)M
-10
0.5t
c(SPC)M
-10
ns
10
t
su(SOMI-SPCH)M
35
35
ns
t
su(SOMI-SPCL)M
35
35
ns
11
t
v(SPCH-SOMI)M
0.25t
c(SPC)M
-10
0.5t
c(SPC)M
-10
ns
t
v(SPCL-SOMI)M
0.25
tc(SPC)M
-10
0.5
tc(SPC)M
-10
ns
(1)
(2)
(3)
The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.
t
= SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25 MHz MAX, master mode receive 12.5 MHz MAX
Slave mode transmit 12.5 MHz MAX, slave mode receive 12.5 MHz MAX.
t
= LSPCLK cycle time
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
(4)
(5)
Submit Documentation Feedback
相關(guān)PDF資料
PDF描述
TMX320F28044GGMQ Digital Signal Processor
TMX320F28044GGMS Digital Signal Processor
TMX320F28044PZQ Digital Signal Processor
TMX320F28044PZS Digital Signal Processor
TMX320F28044ZGMQ Digital Signal Processor
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TMS320F28045PZA 制造商:Texas Instruments 功能描述:- Trays
TMS320F28045PZS 制造商:Texas Instruments 功能描述:- Trays
TMS320F28050PNQ 制造商:Texas Instruments 功能描述:GIZMO
TMS320F28050PNS 制造商:Texas Instruments 功能描述:GIZMO
TMS320F28050PNT 制造商:Texas Instruments 功能描述:GIZMO
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*