參數(shù)資料
型號： TMS320F28044ZGMQ
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Digital Signal Processor
中文描述： 數(shù)字信號處理器
文件頁數(shù)： 78/107頁
文件大?。?/td> 784K
代理商： TMS320F28044ZGMQ
www.ti.com
6.7
Clock Requirements and Characteristics
TMS320F28044
Digital Signal Processor
SPRS357B–AUGUST 2006–REVISED MAY 2007
Table 6-4. Input Clock Frequency
PARAMETER
Resonator (X1/X2)
Crystal (X1/X2)
External oscillator/clock source (XCLKIN or X1 pin)
MIN
20
20
TYP
MAX
UNIT
35
35
f
x
Input clock frequency
MHz
4
100
f
l
Limp mode SYSCLKOUT frequency range (with /2 enabled)
1-5
MHz
Table 6-5. XCLKIN
(1)
Timing Requirements - PLL Enabled
NO.
C8
C9
C10
C11
C12
MIN
33.3
MAX
200
UNIT
ns
ns
ns
%
%
t
c(CI)
t
f(CI)
t
r(CI)
t
w(CIL)
t
w(CIH)
Cycle time, XCLKIN
Fall time, XCLKIN
Rise time, XCLKIN
Pulse duration, XCLKIN low as a percentage of t
c(OSCCLK)
Pulse duration, XCLKIN high as a percentage of t
c(OSCCLK)
This applies to the X1 pin also.
6
6
45
45
55
55
(1)
Table 6-6. XCLKIN
(1)
Timing Requirements - PLL Disabled
NO.
C8
C9
MIN
10
MAX
250
UNIT
ns
ns
ns
ns
ns
%
%
t
c(CI)
t
f(CI)
Cycle time, XCLKIN
Fall time, XCLKIN
Up to 20 MHz
20 MHz to 100 MHz
Up to 20 MHz
20 MHz to 100 MHz
6
2
6
2
C10
t
r(CI)
Rise time, XCLKIN
C11
C12
t
w(CIL)
t
w(CIH)
Pulse duration, XCLKIN low as a percentage of t
c(OSCCLK)
Pulse duration, XCLKIN high as a percentage of t
c(OSCCLK)
This applies to the X1 pin also.
45
45
55
55
(1)
The possible configuration modes are shown in
Table 3-13
.
Table 6-7. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
(1)(2)
NO.
C1
C3
C4
C5
C6
PARAMETER
MIN
10
TYP
MAX
UNIT
ns
ns
ns
ns
ns
cycles
t
c(XCO)
t
f(XCO)
t
r(XCO)
t
w(XCOL)
t
w(XCOH)
t
p
Cycle time, XCLKOUT
Fall time, XCLKOUT
Rise time, XCLKOUT
Pulse duration, XCLKOUT low
Pulse duration, XCLKOUT high
PLL lock time
2
2
H-2
H-2
H+2
H+2
131072t
c(OSCCLK)(3)
(1)
(2)
(3)
A load of 40 pF is assumed for these parameters.
H = 0.5t
OSCCLK is either the output of the on-chip oscillator or the output from an external oscillator.
Electrical Specifications
78
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