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TMS320F28044
Digital Signal Processor
SPRS357B–AUGUST 2006–REVISED MAY 2007
Table 3-1. Addresses of Flash Sectors
ADDRESS RANGE
0x3E 8000 - 0x3E BFFF
0x3E C000 - 0x3E FFFF
0x3F 0000 - 0x3F 3FFF
0x3F 4000 - 0x3F 7F7F
PROGRAM AND DATA SPACE
Sector D (16K x 16)
Sector C (16K x 16)
Sector B (16K x 16)
Sector A (16K x 16)
Program to 0x0000 when using the
Code Security Module
Boot-to-Flash Entry Point
(program branch instruction here)
Security Password (128-Bit)
(Do not program to all zeros)
0x3F 7F80 - 0x3F 7FF5
0x3F 7FF6 - 0x3F 7FF7
0x3F 7FF8 - 0x3F 7FFF
Peripheral Frame 1 and Peripheral Frame 2 are grouped together so as to enable these blocks to be
write/read peripheral block protected. The protected mode ensures that all accesses to these blocks
happen as written. Because of the C28x pipeline, a write immediately followed by a read, to different
memory locations, will appear in reverse order on the memory bus of the CPU. This can cause problems
in certain peripheral applications where the user expected the write to occur first (as written). The C28x
CPU supports a block protection mode where a region of memory can be protected so as to make sure
that operations occur as written (the penalty is extra cycles are added to align the operations). This mode
is programmable and by default, it will protect the selected zones.
The wait-states for the various spaces in the memory map area are listed in
Table 3-2
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Functional Overview
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