參數(shù)資料
型號: TMS320AV411
廠商: Texas Instruments, Inc.
英文描述: Digital NTSC/PAL Encoder(數(shù)字NTSC/PAL編碼器)
中文描述: 數(shù)字的NTSC / PAL編碼器(數(shù)字的NTSC / PAL編碼器)
文件頁數(shù): 9/33頁
文件大?。?/td> 634K
代理商: TMS320AV411
TMS320AV410, TMS320AV411
DIGITAL NTSC/PAL ENCODER
SCSS020B – JULY 1996 – REVISED MAY 1997
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
dual clock system using internal PLL
Figure 4 shows the configuration for the dual clock system using the internal PLL. The internal synchronization
mode of the ’AV410/411 is active. To enable the ’AV410/411 for a 28.6-MHz clock, first enable the PLL via the
PLLEN control bit, then enter the proper selection to the CLKSEL1:0 bits. To select the 27-MHz clock, enter the
proper value for the CLKSEL1:0 bits, then disable the PLL via the PLLEN control bit. This configuration is not
available in stand-alone mode.
’AV410/411
EXTEN
CLK0
OSCIN
CLKBIN
L
Clock Output
Crystal or External Source (27 MHz)
External Connection
CLKBOUT
Figure 4. Dual Clock System Using Internal PLL
external synchronization mode
Figure 5 shows the configuration for the ’AV410/411 operating in external synchronization mode. CLK0 is an
input to the device in this arrangement. Note that VSYNC and HSYNC are also required inputs in this mode.
’AV410/411
EXTEN
CLK0
OSCIN
CLKBIN
H
External Clock
L
L
Figure 5. External Synchronization Mode
P
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