參數(shù)資料
型號(hào)： TMS320AV410
廠(chǎng)商： Texas Instruments, Inc.
英文描述： Digital NTSC/PAL Encoder(數(shù)字NTSC/PAL編碼器)
中文描述： 數(shù)字的NTSC / PAL編碼器（數(shù)字的NTSC / PAL編碼器）
文件頁(yè)數(shù)： 8/33頁(yè)
文件大?。?/td> 634K
代理商： TMS320AV410
TMS320AV410, TMS320AV411
DIGITAL NTSC/PAL ENCODER
SCSS020B – JULY 1996 – REVISED MAY 1997
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
’AV410/411 clock arrangements
The ’AV410/411 has various clock modes available. Choice of the particular mode depends upon the clocking
schemes and host interface available in the system.
single-clock system
Figure 2 shows the configuration for the single-clock (27 or 28.6 MHz) system. The internal synchronization
mode is also active for the ’AV410/411. Selection of clock frequency must be identified using the CLKSEL pin
(stand-alone mode) or the CLKSEL0 bit in the VID1 register (simple serial or I
2
C host interface modes).
’AV410/411
EXTEN
CLK0
OSCIN
CLKBIN
L
Clock Output
Crystal or External Source (27 or 28.6 MHz)
L
Figure 2. Single-Clock System
dual clock system without internal PLL
Figure 3 shows the configuration for the dual clock (27 and 28.6 MHz) system. The internal synchronization
mode is also active for the ’AV410/411, but the internal PLL is not active. Selection between the two clocks is
made by entering 00 or 11 to the CLKSEL1:0 bits in the VID1 register. This configuration is not available when
using the stand-alone mode.
’AV410/411
EXTEN
CLK0
OSCIN
CLKBIN
L
Clock Output
Crystal or External Source (27 MHz)
External Source (28.6 MHz)
Figure 3. Dual Clock System Without PLL
P
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