參數(shù)資料
型號(hào)： TMS320AV410
廠商： Texas Instruments, Inc.
英文描述： Digital NTSC/PAL Encoder(數(shù)字NTSC/PAL編碼器)
中文描述： 數(shù)字的NTSC / PAL編碼器（數(shù)字的NTSC / PAL編碼器）
文件頁(yè)數(shù)： 4/33頁(yè)
文件大小： 634K
代理商： TMS320AV410
TMS320AV410, TMS320AV411
DIGITAL NTSC/PAL ENCODER
SCSS020B – JULY 1996 – REVISED MAY 1997
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
67
AS
I
When IFMOD1 is low and IFMOD0 is low (I2C host interface mode), AS operates as the I2C slave
address select input. When AS is low, the ’AV410/411 I2C slave address is 88h. When AS is high,
the slave address is 8Ch.
BIAS0
80
I
DAC0 bias terminal
BIAS1
82
DAC1 bias terminal
BIAS2
84
DAC2 bias terminal
CLK0
24
I/O
When EXTEN is low, CLK0 is the clock output used to clock pixel data out from the system video
decoder device. Typically, CLK0 outputs at 27 MHz or 28.6 MHz, as determined by the settings of
the OSCIN and CLKBIN pins and the setting of the CLKSEL pin or the CLKSEL 1:0 register bit
values. When EXTEN is high, CLK0 is the external clock input.
CLKBIN
6
I
Secondary system clock input for a dual clock system. In a dual clock system, CLKBIN has a
28.6-MHz clock source as its input. This clock source may originate external to the ’AV410/411 or
may be obtained from the ’AV410/411 internal phase-locked loop (PLL). When using the internal
PLL, CLKBIN should be tied to the CLKBOUT terminal. For a single-clock system, CLKBIN should
be tied low.
CLKBOUT
5
O
Internal PLL clock output terminal. CLKBOUT should be tied to CLKBIN when using the internal
PLL to generate the 28.6-MHz system clock. This function is not available in stand-alone mode.
CLK1OUT
62
O
Alternate pixel clock output which clocks at one-half the system clock frequency. CLK1OUT clock
frequency is either 13.5 MHz or 14.3 MHz.
CLKSEL
71
I
When IFMOD1 is high (stand-alone mode), CLKSEL selects the expected system clock frequency
for the ’AV410/411. If CLKSEL is low, system clock frequency is 27 MHz; if CLKSEL is high,
frequency is 28.6 MHz. When IFMOD1 is low, CLKSEL should be tied low.
COMP0
79
I
DAC0 compensation capacitor
COMP1
81
DAC1 compensation capacitor
COMP2
83
DAC2 compensation capacitor
CS
67
I
Chip select for the simple serial host interface mode (IFMOD1 low and IFMOD0 high).
CSYNC
94
O
Composite sync output, active low
P
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