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參數(shù)資料
| 型號(hào)： | TMS28F004AMB60CDBJL |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 524288 BY 8-BIT/262144 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES |
| 中文描述： | 524288按8-BIT/262144由16位自動(dòng)選擇啟動(dòng)塊閃存 |
| 文件頁(yè)數(shù)： | 40/80頁(yè) |
| 文件大?。?/td> | 1080K |
| 代理商： | TMS28F004AMB60CDBJL |
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TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/
262
144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
40
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
timing requirements for TMS28F004AEy and TMS28F400AEy
write/erase operations — W-controlled writes
ALT.
’28F004AEy60
’28F400AEy60
SYMBOL
3-V VCC
RANGE
5-V VCC
RANGE
UNIT
MIN
MAX
MIN
MAX
tc(W)
tc(W)OP
tc(W)ERB
tc(W)ERP
tc(W)ERM
td(RPR)
th(A)
th(D)
th(E)
th(VPP)
th(RP)
th(WP)
tsu(WP)
tsu(A)
tsu(D)
tsu(E)
tsu(RP)
tsu(VPP)1
tw(W)
tw(WH)
trec(RPHW)
NOTE 15: A–1–A17 for byte-wide
Cycle time, write
tAVAV
tWHQV1
tWHQV2
tWHQV3
tWHQV4
tPHBR
tWHAX
tWHDX
tWHEH
tQVVL
tQVPH
tWHPL
tELPH
tAVWH
tDVWH
tELWL
tPHHWH
tVPWH
tWLWH
tWHWL
tPHWL
110
60
ns
μ
s
s
Cycle time, duration of programming operation
6
6
Cycle time, erase operation (boot block)
0.3
0.3
Cycle time, erase operation (parameter block)
0.3
0.3
s
Cycle time, erase operation (main block)
0.6
0.6
s
Delay time, boot-block relock
200
100
ns
Hold time, A0–A17 (see Note 15)
0
0
ns
Hold time, DQ valid
0
0
ns
Hold time, E
0
0
ns
Hold time, VPP from valid status register bit
Hold time, RP at VHH from valid status register bit
Hold time, WP from valid status register bit
0
0
ns
0
0
ns
0
0
ns
Setup time, WP before write operation
90
50
ns
Setup time, A0–A17 (see Note 15)
90
50
ns
Setup time, DQ
90
50
ns
Setup time, E before write operation
0
0
ns
Setup time, RP at VHH to W going high
Setup time, VPP to W going high
Pulse duration, W low
200
100
ns
200
100
ns
90
50
ns
Pulse duration, W high
20
10
ns
Recovery time, RP high to W going low
800
450
ns
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