參數(shù)資料
型號(hào)： TMP320F28044PZA
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： Digital Signal Processor
中文描述： 數(shù)字信號(hào)處理器
文件頁數(shù)： 28/107頁
文件大小： 784K
代理商： TMP320F28044PZA
www.ti.com
3.2.16
Peripheral Frames 0, 1, 2 (PFn)
3.2.17
General-Purpose Input/Output (GPIO) Multiplexer
3.2.18
32-Bit CPU-Timers (0, 1, 2)
3.2.19
Control Peripherals
TMS320F28044
Digital Signal Processor
SPRS357B–AUGUST 2006–REVISED MAY 2007
The F28044 device segregates peripherals into three sections. The mapping of peripherals is as follows:
PF0:
PIE:
Flash:
Timers:
CSM:
ADC:
GPIO:
ePWM:
SYS:
SCI:
SPI:
ADC:
I
2
C:
PIE Interrupt Enable and Control Registers Plus PIE Vector Table
Flash Control, Programming, Erase, Verify Registers
CPU-Timers 0, 1, 2 Registers
Code Security Module KEY Registers
ADC Result Registers (dual-mapped)
GPIO MUX Configuration and Control Registers
Enhanced Pulse Width Modulator Module and Registers
System Control Registers
Serial Communications Interface (SCI) Control and RX/TX Registers
Serial Port Interface (SPI) Control and RX/TX Registers
ADC Status, Control, and Result Register
Inter-Integrated Circuit Module and Registers
PF1:
PF2:
Most of the peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. This
enables the user to use a pin as GPIO if the peripheral signal or function is not used. On reset, GPIO pins
are configured as inputs. The user can individually program each pin for GPIO mode or peripheral signal
mode. For specific inputs, the user can also select the number of input qualification cycles. This is to filter
unwanted noise glitches. The GPIO signals can also be used to bring the device out of specific low-power
modes.
CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock
prescaling. The timers have a 32-bit count down register, which generates an interrupt when the counter
reaches zero. The counter is decremented at the CPU clock speed divided by the prescale value setting.
When the counter reaches zero, it is automatically reloaded with a 32-bit period value. CPU-Timer 2 is
reserved for Real-Time OS (RTOS)/BIOS applications. CPU-Timer 1 is also reserved for TI system
functions. CPU-Timer 2 is connected to INT14 of the CPU. CPU-Timer 1 can be connected to INT13 of
the CPU. CPU-Timer 0 is for general use and is connected to the PIE block.
The F28044 device supports the following peripherals which are used for embedded control and
communication:
ePWM:
The enhanced PWM peripheral supports independent/complementary PWM generation,
adjustable dead-band generation for leading/trailing edges, latched/cycle-by-cycle trip
mechanism. Some of the PWM pins support HRPWM features.
The ADC block is a 12-bit converter, single ended, 16-channels. It contains two
sample-and-hold units for simultaneous sampling.
ADC:
Functional Overview
28
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