參數(shù)資料
型號(hào)： TMP320F28044PZA
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： Digital Signal Processor
中文描述： 數(shù)字信號(hào)處理器
文件頁數(shù)： 23/107頁
文件大?。?/td> 784K
代理商： TMP320F28044PZA
www.ti.com
3.2
Brief Descriptions
3.2.1
C28x CPU
3.2.2
Memory Bus (Harvard Bus Architecture)
TMS320F28044
Digital Signal Processor
SPRS357B–AUGUST 2006–REVISED MAY 2007
Table 3-2. Wait-states
AREA
WAIT-STATES
0-wait
0-wait
0-wait (writes)
2-wait (reads)
0-wait (writes)
2-wait (reads)
0-wait
COMMENTS
Fixed
Fixed
M0 and M1 SARAMs
Peripheral Frame 0
Peripheral Frame 1
Fixed.
Peripheral Frame 2
Fixed
L0 & L1 SARAMs
Programmed via the Flash registers. 1-wait-state operation
is possible at a reduced CPU frequency. See Section
Section 3.2.5
for more information.
Programmed via the Flash registers. 0-wait-state operation
is possible at reduced CPU frequency. The CSM password
locations are hardwired for 16 wait-states. See Section
Section 3.2.5
for more information.
Fixed
Programmable,
1-wait minimum
OTP
Programmable,
0-wait minimum
Flash
Boot-ROM
1-wait
The C28x DSP generation is the newest member of the TMS320C2000 DSP platform. The C28x is a
very efficient C/C++ engine, hence enabling users to develop not only their system control software in a
high-level language, but also enables math algorithms to be developed using C/C++. The C28x is as
efficient in DSP math tasks as it is in system control tasks that typically are handled by microcontroller
devices. This efficiency removes the need for a second processor in many systems. The 32 x 32-bit MAC
capabilities of the C28x and its 64-bit processing capabilities, enable the C28x to efficiently handle higher
numerical resolution problems that would otherwise demand a more expensive floating-point processor
solution. Add to this the fast interrupt response with automatic context save of critical registers, resulting in
a device that is capable of servicing many asynchronous events with minimal latency. The C28x has an
8-level-deep protected pipeline with pipelined memory accesses. This pipelining enables the C28x to
execute at high speeds without resorting to expensive high-speed memories. Special branch-look-ahead
hardware minimizes the latency for conditional discontinuities. Special store conditional operations further
improve performance.
As with many DSP type devices, multiple busses are used to move data between the memories and
peripherals and the CPU. The C28x memory bus architecture contains a program read bus, data read bus
and data write bus. The program read bus consists of 22 address lines and 32 data lines. The data read
and write busses consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable
single cycle 32-bit operations. The multiple bus architecture, commonly termed "Harvard Bus", enables the
C28x to fetch an instruction, read a data value and write a data value in a single cycle. All peripherals and
memories attached to the memory bus will prioritize memory accesses. Generally, the priority of memory
bus accesses can be summarized as follows:
Highest:
Data Writes
Program Writes
Data Reads
Program Reads
Fetches
(Simultaneous data and program writes cannot occur on the memory bus.)
(Simultaneous data and program writes cannot occur on the memory bus.)
(Simultaneous program reads and fetches cannot occur on the memory bus.)
(Simultaneous program reads and fetches cannot occur on the memory bus.)
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Functional Overview
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