- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384019 > TMP320F28044GGMA (Texas Instruments, Inc.) Digital Signal Processor PDF資料下載
參數(shù)資料
| 型號(hào)： | TMP320F28044GGMA |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | Digital Signal Processor |
| 中文描述： | 數(shù)字信號(hào)處理器 |
| 文件頁數(shù)： | 87/107頁 |
| 文件大?。?/td> | 784K |
| 代理商： | TMP320F28044GGMA |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁當(dāng)前第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁
www.ti.com
t
d(IDLEXCOL)
X1/X2
or XCLKIN
XCLKOUT
HALT
HALT
Wake-up Latency
Flushing Pipeline
t
d(WAKEHALT)
(A)
(B)
(C)
(D)
Device
Status
(E)
(G)
(F)
PLL Lock-up Time
Normal
Execution
t
w(WAKE-GPIO)
t
p
GPIOn
Oscillator Start-up Time
TMS320F28044
Digital Signal Processor
SPRS357B–AUGUST 2006–REVISED MAY 2007
Table 6-17. HALT Mode Switching Characteristics
PARAMETER
MIN
TYP
MAX
UNIT
cycles
cycles
t
d(IDLE-XCOL)
t
p
Delay time, IDLE instruction executed to XCLKOUT low
PLL lock-up time
Delay time, PLL lock to program execution resume
Wake up from flash
–
Flash module in sleep state
32t
c(SCO)
45t
c(SCO)
131072t
c(OSCCLK)
1125t
c(SCO)
cycles
t
d(WAKE-HALT)
35t
c(SCO)
cycles
Wake up from SARAM
A.
B.
IDLE instruction is executed to put the device into HALT mode.
The PLL block responds to the HALT signal. SYSCLKOUT is held for approximately 32 cycles before the oscillator is
turned off and the CLKIN to the core is stopped. This 32-cycle delay enables the CPU pipe and any other pending
operations to flush properly.
Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as
the clock source, the internal oscillator is shut down as well. The device is now in HALT mode and consumes
absolute minimum power.
When the GPIOn pin is driven low, the oscillator is turned on and the oscillator wake-up sequence is initiated. The
GPIO pin should be driven high only after the oscillator has stabilized. This enables the provision of a clean clock
signal during the PLL lock sequence. Since the falling edge of the GPIO pin asynchronously begins the wakeup
procedure, care should be taken to maintain a low noise environment prior to entering and during HALT mode.
When GPIOn is deactivated, it initiates the PLL lock sequence, which takes 131,072 OSCCLK (X1/X2 or X1 or
XCLKIN) cycles.
When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after a latency. The HALT
mode is now exited.
Normal operation resumes.
C.
D.
E.
F.
G.
Figure 6-12. HALT Wake-Up Using GPIOn
Submit Documentation Feedback
Electrical Specifications
87
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TMP320F28044GGMS | Digital Signal Processor |
| TMP320F28044PZA | Digital Signal Processor |
| TMP320F28044PZQ | Digital Signal Processor |
| TMP320F28044PZS | Digital Signal Processor |
| TMP320F28044ZGMA | Digital Signal Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMP320F28044GGMQ | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Digital Signal Processor |
| TMP320F28044GGMS | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Digital Signal Processor |
| TMP320F28044PZA | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Digital Signal Processor |
| TMP320F28044PZQ | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Digital Signal Processor |
| TMP320F28044PZS | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Digital Signal Processor |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。