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TMS320F28044
Digital Signal Processor
SPRS357B–AUGUST 2006–REVISED MAY 2007
List of Figures
2-1
100-Pin PZ LQFP (Top View)
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12
100-Ball GGM and ZGM MicroStar BGA (Bottom View)
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13
Functional Block Diagram
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20
F28044 Memory Map
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21
External and PIE Interrupt Sources
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31
Multiplexing of Interrupts Using the PIE Block
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32
Clock and Reset Domains
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34
OSC and PLL Block Diagram
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36
Using a 3.3-V External Oscillator
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36
Using a 1.8-V External Oscillator
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36
Using the Internal Oscillator
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36
Watchdog Module
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39
CPU-Timers
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41
CPU-Timer Interrupt Signals and Output Signal
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42
Multiple PWM Modules
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43
ePWM Sub-Modules Showing Critical Internal Signal Interconnections
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48
Block Diagram of the ADC Module
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50
ADC Pin Connections With Internal Reference
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51
ADC Pin Connections With External Reference
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52
Serial Communications Interface (SCI) Module Block Diagram
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56
SPI Module Block Diagram (Slave Mode)
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59
I
2
C Peripheral Module Interfaces
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61
GPIO MUX Block Diagram
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62
Qualification Using Sampling Window
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65
Example of TMS320x280x Device Nomenclature
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67
Emulator Connection Without Signal Buffering for the DSP
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75
3.3-V Test Load Circuit
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77
Clock Timing
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79
Power-on Reset
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80
Warm Reset
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81
Example of Effect of Writing Into PLLCR Register
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82
General-Purpose Output Timing
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82
Sampling Mode
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83
General-Purpose Input Timing
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84
IDLE Entry and Exit Timing
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85
STANDBY Entry and Exit Timing Diagram
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86
HALT Wake-Up Using GPIOn
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87
PWM Hi-Z Characteristics
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88
ADCSOCAO or ADCSOCBO Timing
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89
2-2
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
5-1
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
List of Figures
4
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