參數(shù)資料
型號(hào): TMP320C6205GHKA200
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號(hào)處理
英文描述: FIXED-POINT DIGITAL SIGNAL PROCESSOR
中文描述: 定點(diǎn)數(shù)字信號(hào)處理器
文件頁(yè)數(shù): 41/72頁(yè)
文件大小: 1143K
代理商: TMP320C6205GHKA200
SPRS106G OCTOBER 1999 REVISED JULY 2006
41
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
SYNCHRONOUS-BURST MEMORY TIMING
timing requirements for synchronous-burst SRAM cycles (see Figure 19)
NO.
200
UNIT
MIN
MAX
7
tsu(EDV-CKO2H)
th(CKO2H-EDV)
Setup time, read EDx valid before CLKOUT2 high
2.5
ns
8
Hold time, read EDx valid after CLKOUT2 high
1.5
ns
switching characteristics over recommended operating conditions for synchronous-burst SRAM
cycles
(see Figure 19 and Figure 20)
NO.
PARAMETER
200
UNIT
MIN
MAX
1
tosu(CEV-CKO2H)
toh(CKO2H-CEV)
tosu(BEV-CKO2H)
toh(CKO2H-BEIV)
tosu(EAV-CKO2H)
toh(CKO2H-EAIV)
tosu(ADSV-CKO2H)
toh(CKO2H-ADSV)
tosu(OEV-CKO2H)
toh(CKO2H-OEV)
tosu(EDV-CKO2H)
toh(CKO2H-EDIV)
tosu(WEV-CKO2H)
toh(CKO2H-WEV)
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses.
§For the first write in a series of one or more consecutive adjacent writes, the write data is generated one CLKOUT2 cycle early to accommodate
the ED enable time.
Output setup time, CEx valid before CLKOUT2 high
P 0.8
ns
2
Output hold time, CEx valid after CLKOUT2 high
P 4
ns
3
Output setup time, BEx valid before CLKOUT2 high
P 0.8
ns
4
Output hold time, BEx invalid after CLKOUT2 high
P 4
ns
5
Output setup time, EAx valid before CLKOUT2 high
P 0.8
ns
6
Output hold time, EAx invalid after CLKOUT2 high
P 4
ns
9
Output setup time, SDCAS/SSADS valid before CLKOUT2 high
P 0.8
ns
10
Output hold time, SDCAS/SSADS valid after CLKOUT2 high
P 4
ns
11
Output setup time, SDRAS/SSOE valid before CLKOUT2 high
P 0.8
ns
12
Output hold time, SDRAS/SSOE valid after CLKOUT2 high
Output setup time, EDx valid before CLKOUT2 high§
P 4
ns
13
P 1
ns
14
Output hold time, EDx invalid after CLKOUT2 high
P 4
ns
15
Output setup time, SDWE/SSWE valid before CLKOUT2 high
P 0.8
ns
16
Output hold time, SDWE/SSWE valid after CLKOUT2 high
P 4
ns
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