參數(shù)資料
型號(hào)： TMP320C6205GHKA200
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： FIXED-POINT DIGITAL SIGNAL PROCESSOR
中文描述： 定點(diǎn)數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 14/72頁(yè)
文件大?。?/td> 1143K
代理商： TMP320C6205GHKA200
SPRS106G OCTOBER 1999 REVISED JULY 2006
14
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
Signal Descriptions
SIGNAL
TYPE
DESCRIPTION
NAME
NO.
CLOCK/PLL
CLKIN
J3
I
Clock Input
CLKOUT2
T19
O
Clock output at half of device speed
Used for synchronous memory interface
CLKMODE0
L3
I
Clock mode select 0
Selects whether the on-chip PLL is used or bypassed. For more details, see the
Clock PLL
section.
The PLL Multiply Factor is selected at boot configuration. For more details, see the EMIF Data
pin descriptions and the clock PLL section.
PLLV
PLLG
PLLF
K5
A§
A§
A§
PLL analog VCC connection for the low-pass filter
PLL analog GND connection for the low-pass filter
L2
L1
PLL low-pass filter connection to external components and a bypass capacitor
JTAG EMULATION
TMS
E17
I
JTAG test-port mode select (features an internal pullup)
TDO
D19
O/Z
JTAG test-port data out
TDI
D18
I
JTAG test-port data in (features an internal pullup)
TCK
D17
I
JTAG test-port clock
TRST
C19
I
JTAG test-port reset (features an internal pulldown)
Emulation pin 1, pullup with a dedicated 20-k
resistor
Emulation pin 0, pullup with a dedicated 20-k
resistor
RESET AND INTERRUPTS
EMU1
E18
I/O/Z
EMU0
F15
I/O/Z
RESET
C3
I
Device reset
NMI
A8
I
Nonmaskable interrupt
Edge-driven (rising edge)
EXT_INT7
B15
External interrupts
Edge-driven
Polarity independently selected via the External Interrupt Polarity Register bits (EXTPOL.[3:0])
EXT_INT6
C15
I
EXT_INT5
A16
EXT_INT4
B16
IACK
A15
O
Interrupt acknowledge for all active interrupts serviced by the CPU
INUM3
F12
Active interrupt identification number
Valid during IACK for all active interrupts (not just external)
Encoding order follows the interrupt-service fetch-packet ordering
INUM2
A14
O
INUM1
B14
INUM0
C14
POWER-DOWN STATUS
PD
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
PLLV, PLLG, and PLLF are not part of external voltage supply or ground. See the
clock PLL
section for information on how to connect these pins.
§A = Analog Signal (PLL Filter)
For emulation and normal operation, pull up EMU1 and EMU0 with a dedicated 20-k
resistor. For boundary scan, pull down EMU1 and EMU0
with a dedicated 20-k
resistor.
B18
O
Power-down modes 2 or 3 (active if high)
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