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參數(shù)資料
| 型號(hào)： | TMC2491A |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Multistandard Digital Video Encoder(多標(biāo)準(zhǔn)數(shù)字視頻編碼器) |
| 中文描述： | 多標(biāo)準(zhǔn)數(shù)字視頻編碼器（多標(biāo)準(zhǔn)數(shù)字視頻編碼器） |
| 文件頁數(shù)： | 9/36頁 |
| 文件大?。?/td> | 208K |
| 代理商： | TMC2491A |
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PRODUCT SPECIFICATION
TMC2490A/TMC2491A
9
Control Register Definitions
(continued)
General Control Register (0F)
7
6
5
4
3
2
1
0
PED21
Reserved
VSEL
CBSEL
VBIEN
Reserved
Reg
0F
Bit
7
Name
PED21
Description
VBI Pedestal Enable.
When HIGH and FORMAT is 00 (NTSC) or 10
(PAL-M), pedestal is added to lines 21, 22, 283, 284, 285. When LOW, no
pedestal is placed on these lines. PED21 is valid for NTSC and PAL-M only
and should be LOW for all other formats.
Program HIGH.
Vertical Sync Select.
When LOW, the TMC2490(1)A outputs a traditional
vertical sync on VSYNC. When HIGH, the chip outputs odd/even field
identification on the VSYNC pin, with 0 denoting an odd field.
CBSEL/PDC pin function.
When CBSEL = 0, the PDC signal is produced
on the CBSEL/PCD pin. When CBSEL = 1, the CBSEL signal is produced
on the CBSEL/PDC pin.
VBI Pixel Data Enable.
When VBIEN = 0, the vertical interval lines are
blanked. When VBIEN = 1, Pixel data is encoded into the VBI lines.
Program LOW.
Sync Delay. HDEL shifts the falling edge of the H and V syncs relative to the
PD port.
0F
0F
6
5
Reserved
VSEL
0F
4
CBSEL
0F
3
VBIEN
0F
0F
2
1–0
Reserved
HDEL
HDEL Result
00
01
H and V syncs are aligned with luminance pixel 735 (Y735)
H and V syncs are aligned with Blue color difference pixel 735
(Cb736)
H and V syncs are aligned with luminance pixel 736 (Y736)
H and V syncs are aligned with Red color difference pixel 735
(Cr736)
10
11
Refer to Figure 2a, HDEL Timing
Reserved Registers (10–1F)
7
6
5
4
3
2
1
0
Reserved
Reg
10–
1F
Bit
7–0
Name
Reserved
Description
May be left unprogrammed
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