參數(shù)資料
型號: TMC2491A
廠商: Fairchild Semiconductor Corporation
英文描述: Multistandard Digital Video Encoder(多標(biāo)準(zhǔn)數(shù)字視頻編碼器)
中文描述: 多標(biāo)準(zhǔn)數(shù)字視頻編碼器(多標(biāo)準(zhǔn)數(shù)字視頻編碼器)
文件頁數(shù): 3/36頁
文件大?。?/td> 208K
代理商: TMC2491A
PRODUCT SPECIFICATION
TMC2490A/TMC2491A
3
Pin Assignments
Pin Descriptions
Pin Name
Clock
PXCK
Pin Number
Value
Pin Function Description
25
TTL
Pixel Clock Input.
to generate the internal pixel clock. PXCK drives the entire
TMC2490(1)A, except the asynchronous microprocessor
interface. All internal registers are strobed on the rising edge of
PXCK.
This 27.0 MHz clock is internally divided by 2
Data Input Port
PD
7-0
38–44, 3
TTL
Pixel Data Inputs.
PD
7-0
(Figure 1).
Video data enters the TMC2490(1)A on
Microprocessor Interface
D
7-0
9–12, 14–17
TTL
Data I/O, General Purpose I/O, Chroma Input Port.
is HIGH, all control parameters are loaded into and read back
over this 8-bit port. When SER = LOW, D
composite sync output, D
1
outputs a burst flag during the back
porch, D
2-5
are General Purpose Outputs, and D
Purpose Inputs.
Master Reset Input.
Bringing RESET LOW forces the internal
state machines to their starting states and disables all outputs.
Serial/Parallel Port Select.
When SER is LOW, SA
conjunction with SA
0
selects one of four addresses for the
TMC2490(1)A.
Serial/Parallel Port Select.
When SER is LOW, SA
conjunction with SA
1
selects one-of-four addresses for the
TMC2490(1)A. When SER is HIGH, this control governs whether
the parallel microprocessor interface selects a table address or
reads/writes table contents.
When SER
0
can serve as a
6-7
are General
RESET
22
TTL
SA
1
4
TTL
1
in
SA
0
, ADR
5
TTL
0
in
65-2490(1)A-02
SCL/
CS
SER
D
7
D
6
D
5
D
4
GND
D
3
D
2
D
1
D
0
PD
6
PD
7
V
DD
GND
CHROMA
V
DDA
C
BYP
LUMA
GND
COMPOSITE
GND
S
W
S
0
/
S
1
P
0
G
V
D
P
1
P
2
P
3
P
4
P
5
H
V
,
B
C
,
S
R
V
D
G
P
V
D
V
R
R
R
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
1
1
2
2
2
2
2
2
2
2
2
6
5
4
3
2
1
4
4
4
4
4
TMC2490A
TMC2491A
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