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參數(shù)資料
| 型號： | TMC22052AKHC |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | Multistandard Digital Video Decoder Three-Line Adaptive Comb Decoder Family, 8 & 10 bit |
| 中文描述： | COLOR SIGNAL DECODER, PQFP100 |
| 封裝： | MQFP-100 |
| 文件頁數(shù)： | 46/84頁 |
| 文件大?。?/td> | 417K |
| 代理商： | TMC22052AKHC |
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TMC22x5yA
PRODUCT SPECIFICATION
46
REV. 1.0.0 2/4/03
Figure 15. Block Diagram of Comb Filter Input
The primary and secondary inputs are selected within the
input processor. The primary input is normally the undelayed
composite video signal in line, field, and frame based comb
filters or either the luma or chroma channel when processing
YC or D1 signals. The secondary provides the field or frame
delayed composite input for field and frame based comb
filters and the chroma or luma channel when processing YC
or D1 signals.
When implementing a line based comb filter the outputs of
1H bandsplit filter, ie 1HH, 1HL, are delayed through the
second line store, LSTORE2. The number of bits delayed is
dependent upon the type of comb filter being implemented.
For chroma comb filters all the bits of the 1HH signal are
delayed, as this information supplies the outer tap of the
chroma comb filter, while only the upper bits of 1HL are
delayed as this data is used only in the generation of the
luma error signals. In the case of luma combs an equal
number of bits of the 1HH and 1HL signals are delayed and
summed together to produce the 2HF signal for the outer tap
of the luma comb filter. The configuration of LSTORE2 is
determined by the SPLIT register bit.
It is important to note that when implementing a field or
frame based comb filter the secondary input must be selected
by setting the LSIN register bit HIGH, and the first line store,
LSTORE1, must be bypassed by setting the LS1BY register
bit HIGH.
For YC and D1 processing the secondary input bypasses the
comb filter completely and provides the VIDEOB signal
input the 3:1 multiplexer used to select the FLAT signal,
see Figure 16.
LPF
LPF
DELAY
2:1
MUX
2:1
MUX
2:1
MUX
2:1
MUX
LSTORE1
[9:0]
LSTORE2
2HH
LSTORE2
2HX
LSTORE2
2HL
0HF
0HL
0HH
1HF
1HL
1HH
2HH
2HF
2HL
65-22x5y-56
VIDEOB
–
–
+
Primary
Input
Secondary
Input
BSFSEL
BSFSEL
LS1IN
LS1BY
1HH
1HH (lsbs)
1HL
Split
1HL (lsbs)
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參數(shù)描述 |
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| TMC22053AKHC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TMC22053KHC | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Fairchild Semiconductor Corporation 功能描述: |
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| TMC22071AKHC1 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Genlocking Video Digitizer |
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