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參數資料
| 型號： | TLV5580PW |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 8-BIT, 80 MSPS LOW-POWER A/D CONVERTER |
| 中文描述： | 8位，80 MSPS的低功耗A / D轉換器 |
| 文件頁數： | 9/34頁 |
| 文件大小： | 531K |
| 代理商： | TLV5580PW |
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TLV5580
8-BIT, 80 MSPS LOW-POWER A/D CONVERTER
SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating conditions with f
CLK
= 80 MSPS and use
of external voltage references (unless otherwise noted) (continued)
timing requirements
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fclk
fclk
td(o)
th(o)
Maximum conversion rate
80
MHz
Minimum conversion rate
10
kHz
Output delay time (see Figure 1)
CL = 10 pF,
CL = 2 pF,
See Notes 5 and 6
9
ns
Output hold time
See Note 5
2
ns
td(pipe)
Pipeline delay (latency)
See Note 6
4.5
4.5
4.5
CLK
cycles
td(a)
tj(a)
tdis
ten
NOTES:
Aperture delay time
3
ns
Aperture jitter
See Note 5
1.5
ps, rms
Disable time, OE rising to Hi-Z
Enable, OE falling to valid data
5
5
8
8
ns
ns
5. Output timing td(o) is measured from the 1.5 V level of the CLK input falling edge to the 10%/90% level of the digital output. The digital
output load is not higher than 10 pF.
Output hold time th(o) is measured from the 1.5 V level of the CLK input falling edge to the 10%/90% level of the digital output. The
digital output is load is not less than 2 pF.
Aperture delay td(A) is measured from the 1.5 V level of the CLK input to the actual sampling instant.
The OE signal is asynchronous.
OE timing tdis is measured from the VIH(MIN) level of OE to the high-impedance state of the output data. The digital output load is
not higher than 10 pF.
OE timing ten is measured from the VIL(MAX) level of OE to the instant when the output data reaches VOH(min) or VOL(max) output
levels. The digital output load is not higher than 10 pF.
6. The number of clock cycles between conversion initiation on an input sample and the corresponding output data being made
available from the ADC pipeline. Once the data pipeline is full, new valid output data is provided on every clock cycle. In order to
know when data is stable on the output pins, the output delay time td(o) (i.e., the delay time through the digital output buffers) needs
to be added to the pipeline latency. Note that since the max. td(o) is more than 1/2 clock period at 80 MHz; data cannot be reliably
clocked in on a rising edge of CLK at this speed. The falling edge should be used.
D0–D7
N–4
N–3
N–2
N–1
N
N+1
N
N+1
N+2
N+3
N+4
N+5
tj(A)
td(A)
VIL
(max)
1.5 V
tw(CLKH)
tw(CLKL)
1/fCLK
th(o)
1.5 V
td(o)
tdis
ten
CLK
OE
90%
10%
VIH(min)
td(pipe)
VOH(min)
VOL(max)
VIL(max)
VIH
(min)
Figure 1. Timing Diagram
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