參數(shù)資料
型號(hào)： TLV5535PW
廠商： Texas Instruments, Inc.
英文描述： 8-BIT, 35 MSPS, LOW-POWER ANALOG-TO-DIGITAL CONVERTER
中文描述： 8位，35 MSPS的，低功耗模擬數(shù)字轉(zhuǎn)換器
文件頁(yè)數(shù)： 14/32頁(yè)
文件大?。?/td> 535K
代理商： TLV5535PW
TLV5535
8-BIT, 35 MSPS, LOW-POWER ANALOG-TO-DIGITAL CONVERTER
SLAS221 – JUNE 1999
14
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLE OF OPERATION
analog input (continued)
So, for applications running at a lower f
CLK
, the total source resistance will increase proportionally.
AIN
CI
S1
RSW
RS
VS
TLV5535
Figure 12. Simplified Equivalent Input Circuit
dc coupled input
For dc-coupled systems an op amp can level-shift a ground-referenced input signal. A circuit as shown in
Figure 13(a) is acceptable. Alternatively, the user might want a bipolar shift together with the bottom reference
voltage as seen in Figure 13(b). In this case the AIN voltage is given by:
AIN
2
R2
÷
R
1
R2
VREF– VIN
_
+
AVDD
VIN
REFTI
REFTO
REFBI
REFBO
AIN
TLV5535
_
+
VREF
VIN
REFTI
REFTO
REFBI
REFBO
AIN
TLV5535
RIN
R1
RIN
R2
(a)
(b)
Figure 13. DC-Coupled Input Circuit
ac coupled input
For many applications, especially in single supply operation, ac coupling offers a convenient way for biasing
the analog input signal at the proper signal range. Figure 14 shows a typical configuration. To maintain the
outlined specifications, the component values need to be carefully selected. The most important issue is the
positioning of the 3-dB high-pass corner point f
–3 dB
, which is a function of R
2
and the parallel combination of
C
1
and C
2
, called C
eq
. This is given by the following equation:
f–3 dB
1
÷
2
π
x R2x Ceq
where C
eq
is the parallel combination of C
1
and C
2
.
Since C1 is typically a large electrolytic or tantalum capacitor, the impedance becomes inductive at higher
frequencies. Adding a small ceramic or polystyrene capacitor, C2 of approximately 0.01
μ
F, which is not
inductive within the frequency range of interest, maintains low impedance. If the minimum expected input signal
frequency is 20 kHz, and R2 equals 1 k
and R1 equals 50
, the parallel capacitance of C1 and C2 must be
a minimum of 8 nF to avoid attenuating signals close to 20 kHz.
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