參數(shù)資料
型號(hào)： TLV1543M
廠(chǎng)商： Texas Instruments, Inc.
英文描述： 3.3-V 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
中文描述： 3.3 V的10位模擬數(shù)字轉(zhuǎn)換器與串行控制和11個(gè)模擬輸入
文件頁(yè)數(shù)： 8/18頁(yè)
文件大?。?/td> 295K
代理商： TLV1543M
TLV1543C, TLV1543M
3.3-V 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS072C – DECEMBER 1992 – REVISED MARCH 1995
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions
MIN
NOM
3.3
MAX
5.5
UNIT
V
Supply voltage VCC
Supply voltage, VCC
TLV1543C
3
TLV1543M
3
3.3
3.6
V
Positive reference voltage, Vref+ (see Note 2)
Negative reference voltage, Vref– (see Note 2)
Differential reference voltage, Vref+ – Vref– (see Note 2)
Analog input voltage (see Note 2)
VCC
V
0
V
2.5
VCC
VCC+0.2
VCC
V
0
V
High level control input voltage VIH
High-level control input voltage, VIH
TLV1543C
VCC = 3 V to 5.5 V
VCC = 3 V to 3.6 V
VCC = 3 V to 5.5 V
VCC = 3 V to 3.6 V
2
V
TLV1543M
2
V
Low level control input voltage VIL
Low-level control input voltage, VIL
TLV1543C
0.6
V
TLV1543M
0.8
V
Setup time, address bits at data input before I/O CLOCK
↑
, tsu(A) (see Figure 4)
Hold time, address bits after I/O CLOCK
↑
, th(A) (see Figure 4)
Hold time, CS low after last I/O CLOCK
↓
, th(CS)
Setup time, CS low before clocking in first address bit, tsu(CS) (see Note 3)
100
ns
0
ns
0
ns
μ
s
1.425
Clock frequency at I/O CLOCK (see Note 4)
TLC1543C
0
1.1
MHz
TLC1543M
0
2.1
Pulse duration, I/O CLOCK high, twH(I/O)
Pulse duration, I/O CLOCK low, twL(I/O)
Transition time, I/O CLOCK, tt(I/O) (see Note 5)
Transition time, ADDRESS and CS, tt(CS)
190
ns
190
ns
μ
s
μ
s
1
10
Operating free air temperature TA
Operating free-air temperature, TA
TLV1543C
TLV1543M
0
70
125
°
C
–55
NOTES:
2. Analog input voltages greater than that applied to REF+ convert as all ones (1111111111), while input voltages less than that applied
to REF– convert as all zeros (0000000000). The device is functional with reference voltages down to 1 V (Vref+ – Vref–); however,
the electrical specifications are no longer applicable.
3. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system
clock after CS
↓
before responding to control input signals. No attempt should be made to clock in an address until the minimum CS
setup time has elapsed.
4. For 11- to 16-bit transfers, after the tenth I/O CLOCK falling edge (
≤
2 V), at least one I/O clock rising edge (
≥
2 V) must occur within
9.5
μ
s.
5. This is the time required for the clock input signal to fall from VIHmin to VILmax or to rise from VILmax to VIHmin. In the vicinity of
normal room temperature, the devices function with input clock transition time as slow as 1
μ
s for remote data-acquisition
applications where the sensor and the A/D converter are placed several feet away from the controlling microprocessor.
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TLV1543MFK 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:3.3V 10 BIT ANALOG TO DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
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TLV1543MJB 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:3.3V 10 BIT ANALOG TO DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
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