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參數(shù)資料
| 型號： | TLV1543M |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 3.3-V 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS |
| 中文描述： | 3.3 V的10位模擬數(shù)字轉(zhuǎn)換器與串行控制和11個模擬輸入 |
| 文件頁數(shù)： | 10/18頁 |
| 文件大?。?/td> | 295K |
| 代理商： | TLV1543M |
TLV1543C, TLV1543M
3.3-V 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS072C – DECEMBER 1992 – REVISED MARCH 1995
10
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
operating characteristics over recommended operating free-air temperature range,
V
CC
= V
ref+
= 3 V to 5.5 V, I/O CLOCK frequency = 1.1 MHz for the TLV1543C,
V
CC
= V
ref+
= 3 V to 3.6 V, I/O CLOCK frequency = 2.1 MHz for the TLV1543M
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
±
1
±
1
±
1
±
1
UNIT
Linearity error (see Note 6)
LSB
Zero error (see Note 7)
See Note 2
LSB
Full-scale error (see Note 7)
See Note 2
LSB
Total unadjusted error (see Note 8)
LSB
ADDRESS = 1011
512
Self-test output code (see Table 3 and Note 9)
ADDRESS = 1100
0
ADDRESS = 1101
1023
tconv
Conversion time
See Figures 9–14
21
μ
s
tc
Total cycle time (access, sample, and conversion)
See Figures 9–14
and Note 10
21
+10 I/O
CLOCK
periods
μ
s
tacq
Channel acquisition time (sample)
See Figures 9–14
and Note 10
6
I/O
CLOCK
periods
tv
td(I/O-DATA)
td(I/O-EOC)
td(EOC-DATA)
tPZH, tPZL
tPHZ, tPLZ
tr(EOC)
tf(EOC)
tr(bus)
tf(bus)
Valid time, DATA OUT remains valid after I/O CLOCK
↓
Delay time, I/O CLOCK
↓
to DATA OUT valid
Delay time, tenth I/O CLOCK
↓
to EOC
↓
Delay time, EOC
↑
to DATA OUT (MSB)
Enable time, CS
↓
to DATA OUT (MSB driven)
Disable time, CS
↑
to DATA OUT (high impedance)
Rise time, EOC
See Figure 6
10
ns
See Figure 6
240
ns
See Figure 7
70
240
ns
See Figure 8
100
ns
μ
s
ns
See Figure 3
1.3
See Figure 3
150
See Figure 8
300
ns
Fall time, EOC
See Figure 7
300
ns
Rise time, data bus
See Figure 6
300
ns
Fall time, data bus
Delay time, tenth I/O CLOCK
↓
to CS
↓
to abort conversion
(see Note 11)
All typical values are at TA = 25
°
C.
NOTES:
2. Analog input voltages greater than that applied to REF+ convert as all ones (1111111111), while input voltages less than that applied
to REF– convert as all zeros (0000000000). The device is functional with reference voltages down to 1 V (Vref+ – Vref–); however,
the electrical specifications are no longer applicable.
6. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.
7. Zero-scale error is the difference between 0000000000 and the converted output for zero input voltage; full-scale error is the
difference between 1111111111 and the converted output for full-scale input voltage.
8. Total unadjusted error comprises linearity, zero-scale, and full-scale errors.
9. Both the input address and the output codes are expressed in positive logic.
10. I/O CLOCK period = 1/(I/O CLOCK frequency) (see Figure 6).
11. Any transitions of CS are recognized as valid only if the level is maintained for a setup time plus two falling edges of the internal clock
(1.425
μ
s) after the transition.
See Figure 6
300
ns
td(I/O-CS)
9
μ
s
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