參數(shù)資料
型號： TLE2074AMFK
廠商： Texas Instruments, Inc.
英文描述： EXCALIBUR LOW-NOISE HIGH-SPEED JFET-INPUT OPERATIONAL AMPLIFIERS
中文描述： 神劍低噪聲高速JFET輸入運算放大器
文件頁數(shù)： 69/77頁
文件大?。?/td> 1274K
代理商： TLE2074AMFK
TLE207x, TLE207xA, TLE207xY
EXCALIBUR LOW-NOISE HIGH-SPEED
JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS181A – FEBRUARY 1997 – REVISED MARCH 2000
69
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using PSpice
Parts
model generation software. The Boyle
macromodel (see Note 4) and subcircuit Figure 72 were generated using the TLE207x typical electrical and
operating characteristics at T
A
= 25
°
C. Using this information, output simulations of the following key parameters
can be generated to a tolerance of 20% (in most cases):
Unity-gain frequency
Common-mode rejection ratio
Phase margin
DC output resistance
AC output resistance
Short-circuit output current limit
Maximum positive output voltage swing
Maximum negative output voltage swing
Slew rate
Quiescent power dissipation
Input bias current
Open-loop voltage amplification
NOTE 4: G.R. Boyle, B.M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers”, IEEE Journal
of Solid-State Circuits SC-9, 353 (1974).
OUT
+
–
+
–
53
+
–
+
–
+
–
+
–
+
–
+
–
.SUBCKT TLE2074 1 2 3 4 5
C1
11
C2
6
DC
5
DE
54
DLP
90
DLN
92
DP
4
EGND
99
FB
7
+ 5.607E6 –6E6 6E6 6E6 –6E6
GA
6
GCM
0
ISS
3
HLIM
90
J1
11
J2
12
12
7
53
5
91
90
3
0
99
2.2E–12
10.00E–12
DX
DX
DX
DX
DX
POLY (2) (3,0) (4,0) 0 .5 .5
POLY (5) VB VC VE VLP VLN 0
0
6
10
0
2
1
11 12 333.0E–6
10 99 7.43E–9
DC 400.0E–6
VLIM 1K
10 JX
10 JX
RD1
RD2
R01
R02
RP
RSS
VB
VC
VE
VLIM
VLP
VLN
.MODEL DX D (IS=800.0E–18)
.MODEL JX PJF (IS=15.00E–12 BETA=554.5E–6
+ VTO=–.6)
.ENDS
4
4
8
7
3
10
9
3
54
7
91
0
11
12
5
99
4
99
0
53
4
8
0
92
3.003E3
3.003E3
80
80
27.30E3
500.0E3
DC 0
DC 2.20
DC 2.20
DC 0
DC 45
DC 45
VCC+
RP
IN–
2
IN+
1
VCC–
RD1
11
J1
J2
10
RSS
ISS
3
12
RD2
VE
54
DE
DP
VC
DC
C1
R2
6
9
EGND
VB
FB
C2
GCM
GA
VLIM
8
5
RO1
RO2
HLIM
90
DLP
91
DLN
92
VLN
VLP
99
7
4
R2
6
9
100.0E3
Figure 72. Boyle Macromodel and Subcircut
PSpiceand Partsare trademarks of MicroSim Corporation.
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