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參數(shù)資料
| 型號： | TLC34076-170 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Color-Palette(170MHz,與TLC34075兼容，另具24位和16位真彩色模式) |
| 中文描述： | 顏色調色板（170MHz的，與TLC34075兼容，另具24位和16位真彩色模式） |
| 文件頁數(shù)： | 20/60頁 |
| 文件大?。?/td> | 408K |
| 代理商： | TLC34076-170 |
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2–3
chosen clock input is used unmodified as the dot clock (DOTCLK), which represents the pixel rate to the
monitor. The device does, however, allow for user programming of the SCLK and VCLK outputs (shift and
video clocks) via the output clock selection register. The input/output clock selection register formats and
divide ratio selections are shown in Tables 2–3, 2–4, and 2–5.
The ECL input can be used as a differential or single-ended input. If the CLK3 input is used as a single-ended
ECL input, the CLK3 input must be externally terminated to set the input common-mode signal level. This
can be done with a simple resistor divider, as is the case with fully differential ECL.
SCLK is designed to drive the VRAMs directly, and VCLK is designed to work with video control signals such
as BLANK, HSYNC, and VSYNC. While SCLK and VCLK are designed as general-purpose shift clock and
video clock outputs, respectively, they also interface directly with the TMS340x0 GSP family. Even though
SCLK and VCLK can be selected independently, there is still a relationship between the two as discussed
below. Many system considerations have been carefully covered in the design, leaving maximum freedom
to the user.
Internally, both SCLK and VCLK are generated from a common clock counter that increments on the rising
edge of the DOTCLK. Therefore, when VCLK is enabled, it is in phase with SCLK (see Figure 2–1).The
internal clock counter is initialized to zero any time the output clock selection register (bits five, four, two,
one) are all set to ones. This provides a simple mechanism to synchronize multiple video interface palettes,
by providing a known phase relationship for the various system clocks. A write directly to the output clock
selection register can cause this to occur, or any of the various resets (POR, hardware, software – see
section 1.5) can also cause the appropriate bits to be written and the counters to reset. Some means of
disabling the dot-clock input to the part while this reset is occurring must be provided if multiple parts are
to be synchronized. Appendix A discusses the SCLK/VCLK relationship specific to the TMS340x0 graphics
signal processor (GSP).
as an example)
(DOTCLK/2
SCLK
as an example)
(DOTCLK/4
VCLK
DOTCLK
Figure 2–1. DOTCLK/VCLK/SCLK Relationship
Table 2–3. Input Clock Selection Register Format
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