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參數(shù)資料
| 型號： | TLC34076-170 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Color-Palette(170MHz,與TLC34075兼容，另具24位和16位真彩色模式) |
| 中文描述： | 顏色調(diào)色板（170MHz的，與TLC34075兼容，另具24位和16位真彩色模式） |
| 文件頁數(shù)： | 18/60頁 |
| 文件大?。?/td> | 408K |
| 代理商： | TLC34076-170 |
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2–1
2
2.1
The processor interface is controlled by the read and write strobes (RD, WR), four register select terminals
(RS<0:3>), and the 8/6 select terminal. The 8/6 select terminal is used to select between 8- and 6-bit
operation and is provided in order to maintain compatibility with the IMSG176/8 color palette. This operation
is carried out in order to utilize the maximum range of the DACs.
Detailed Description
MPU Interface
The internal register map is shown in Table 2–1. The MPU interface operates asynchronously with data
transfers being synchronized by internal logic. All register locations support read and write operations.
Table 2–1. Internal Register Map
RS1
RS0
REGISTER ADDRESSED BY MPU
L
L
Palette address register – write mode
L
H
Color palette holding register
H
L
Pixel read mask
H
H
Palette address register – read mode
L
L
Reserved
L
H
Reserved
H
L
Reserved
H
H
Reserved
L
L
General control register
L
H
Input clock selection register
H
L
Output clock selection register
H
H
Multiplexer control register
L
L
Palette page register
L
H
Reserved
H
L
Test register
H
H
Reset state
RS3
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
RS2
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
2.2
The color palette RAM is addressed by two internal 8-bit registers, one for reading from the RAM and one
for writing to the RAM. These registers are automatically incremented following a RAM transfer, allowing
the entire palette to be read or written with only one access of the address register. When the address
register increments beyond the last location in the RAM, it is reset to the first location (address 0). Although
all read and write accesses to the RAM are asynchronous to SCLK, VCLK, and the dot clock, they are
performed within one dot clock and so do not cause any noticeable disturbance on the display.
Color Palette RAM
The color palette RAM is 24 bits wide for each location (8 bits each for red, green, and blue). If the 6-bit mode
is chosen (8/6 = low), the two MSBs are still written to the color palette RAM. However, if they are read back
in the 6-bit mode, the two MSBs are set to 0 to maintain compatibility with the IMSG176/8 and BT476/8 color
palettes. The output multiplexer shifts the six LSBs to the six MSB positions, fills the two LSBs with zeros,
then feeds the eight bits to the DAC. With the 8/6 terminal held low, data on the lowest six bits of the data
bus are internally shifted up by two bits to occupy the upper six bits at the output multiplexer, and the bottom
two bits are then zeroed. The test register and the ones accumulation register both take data before the
output multiplexer to give the user the maximum flexibility.
The color palette RAM access methodology is described in the following two sections and is fully compatible
with the IMSG176/8 and BT476/8 color palettes.
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