參數(shù)資料
型號(hào)： TLC320AD535I
廠商： Texas Instruments, Inc.
元件分類： Codec
英文描述： DUAL CHANNEL VOICE/DATA CODEC
中文描述： 雙通道語(yǔ)音/數(shù)據(jù)編解碼器
文件頁(yè)數(shù)： 35/84頁(yè)
文件大小： 447K
代理商： TLC320AD535I
2–20
2.19.2.2
DS13 (R/W Bit)
Reset and power-up procedures set this bit to a 0, placing the device in the write mode. When this bit is set
to 1, however, the previous data content of the register being addressed is read out to the host from DOUT
as the least significant 8 bits of the 16-bit secondary word. The first 8 bits remain set to 0. Reading the data
out is nondestructive, and the contents of the register remain unchanged.
A. Write Mode (DS13 = 0)
Data In. The data word to DIN has the following general format in the write mode.
DS15 DS14 DS13 DS12 DS11 DS10
DS09 DS08
DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00
0
Register Address
Register Data
Control Bits
Data Out. The shift clock shifts out all 0s as the pattern to the host from DOUT.
DS15 DS14 DS13 DS12 DS11 DS10
DS09 DS08
DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
B. Read Mode (DS13 = 1)
Data In. The data word to DIN has the following format to allow a register read. Phase shifts can
also be done in the read mode.
DS15 DS14 DS13 DS12 DS11 DS10
DS09 DS08
DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00
1
Register Address
Ignored
Control Bits
Data Out. The shift clock clocks out the data of the register addressed from DOUT in the read mode in
the 8 LSBs.
DS15 DS14 DS13 DS12 DS11 DS10
DS09 DS08
DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00
0
0
0
0
0
0
0
0
Register Data
2.20 Internal Register Format
2.20.1
Pseudo-Register 0 (No-Op Address)
This address represents a no-operation command. No register I/O operation takes place, so the device can
receive secondary commands for phase adjustment without reprogramming any register. A read of the
no-op is 0. The format of the command word is as follows:
DS15 DS14 DS13 DS12 DS11 DS10
DS09 DS08
DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00
X
0
0
0
0
0
X
X
X
X
X
X
X
X
Control Bits
2.20.2
The following command loads DS07 (MSB) – DS00 into the A register.
Register 1 (A Register)
DS15 DS14 DS13 DS12 DS11 DS10
DS09 DS08
DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00
R/W
0
0
0
1
0
Register Data
Control Bits
The data in DS07 – DS00 determines the division of the master clock to produce the internal FCLK.
FCLK frequency = MCLK/(A register contents
×
2)
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