參數(shù)資料
型號： TLC320AC02I
廠商： Texas Instruments, Inc.
英文描述： Single-Supply Analog Interface Circuit
中文描述： 單電源模擬接口電路
文件頁數(shù)： 31/84頁
文件大?。?/td> 447K
代理商： TLC320AC02I
2–16
DOUT
[ (B register)/2] FCLK Periods
Primary Frame Sync
(16 SCLKs long)
Secondary Frame Sync
(16 SCLKs long)
FS
2s-Complement ADC Output
(14 bits plus 00 for the two LSBs)
16 Bits All 0s, Except When in
Read Mode (then least significant
8 bits are register data)
DIN
2s-Complement Input for the DAC
Channel (14 bits plus two
function bits). If the 2 LSBs Are
Set to 1, Secondary Frame Sync Is
Generated by the TLC320AC02
Input Data for the Internal Registers
(16 bits containing control,
address, and data information)
The time between the primary and secondary frame sync is the time equal to filter clock (FCLK) period multiplied by the
B-register contents divided by two. The time interval is rounded to the nearest shift clock. The secondary frame-sync
signal goes from high to low on the next shift clock low-to-high transition after (B register/2) filter clock periods.
Figure 2–3. Master and Stand-Alone Functional Sequence
2.16.2 Slave and Codec-Mode Word Sequence and Information Content During
Primary and Secondary Communications
For the slave and codec modes, the sequence is basically the same as the stand-alone and master modes
with the exception that the frame sync and the shift clock are generated and controlled externally as shown
in Figure 2–3. For the codec mode, the frame-sync pulse width needs to be a minimum of one shift clock
long. The timing relationship between the frame sync and shift clock is shown in the timing diagrams. Phase
shifting is usually not required in the slave or codec mode because the frame-sync timing can be adjusted
externally if required.
DOUT
Primary Frame Sync
Secondary Frame Sync
FS
2s-Complement ADC Output
(14 bits plus 00 for the 2 LSBs in
master and stand-alone mode and
01 in slave mode)
16 Bits, All 0s, Except When in
Read Mode (then least significant
8 bits are register data)
DIN
2s-Complement Input for the DAC
Channel (14 bits plus two
function bits)
Input Data for the Internal
Registers (16 bits containing
control, address, and data
information)
1 SCLK Minimum
1 SCLK Minimum
NOTE A: The time between the primary and secondary frame syncs is determined by the application; however, enough
time must be provided so that the host can execute the required number of software instructions in the time
between the end of the primary data transfer (rising edge of the primary frame-sync interval) and the falling
edge of the secondary frame sync (start of secondary communications).
Figure 2–4. Slave and Codec Functional Sequence
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