參數(shù)資料
型號： TLC320AC02I
廠商： Texas Instruments, Inc.
英文描述： Single-Supply Analog Interface Circuit
中文描述： 單電源模擬接口電路
文件頁數(shù)： 25/84頁
文件大?。?/td> 447K
代理商： TLC320AC02I
2–10
during DOUT secondary communications by setting the read bit to 1 in the appropriate register. Since the
register is in the read mode, no data can be written to the register during this cycle. To return this register
to the write mode requires a subsequent secondary communication (see Section 2.19 for detailed register
description).
2.12.2
The A counter counts according to the contents of the A register, and the A counter frequency is divided by
two to produce the filter clock (FCLK). The B counter is clocked by FCLK with the following functional
sequence:
Master and Stand-Alone Functional Sequence
1.
The B counter starts counting down from the B register value minus one. Each count remains in
the counter for one FCLK period including the zero count. This total counter time is referred to
as the B cycle. The end of the zero count is called the end of B cycle.
2.
When the B counter gets to a count of nine, the analog-to-digital (A-to-D) conversion starts.
3.
The A-to-D conversion is complete ten FCLK periods later.
4.
FS goes low on a rising edge of SCLK after the A-to-D conversion is complete. That rising edge
of SCLK must be preceded by a falling edge of SCLK, which is the first falling edge to occur after
the end of B cycle.
5.
The D-to-A conversion cycle begins on the rising edge of the internal frame-sync interval and is
complete ten FCLK periods later.
2.13 Slave and Codec Modes
The only difference between the slave and codec modes is that the codec mode is controlled directly by the
host and does not use a delayed frame-sync signal. In both modes, the shift clock and the frame sync are
both externally generated and must be synchronous with MCLK. The conversion frequency is set by the time
interval of externally applied frame-sync falling edges except when the free-run function is selected by bit 5
of register 6 (see Section 2.15.4). The slave device or devices share the shift clock generated by the master
device but receive the frame sync from the previous slave in the chain. The Nth slave FS receives the
(N–1)st slave FSD output and so on. The first slave device in the chain receives FSD from the master.
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