參數(shù)資料
型號(hào)： TLC320AC02I
廠(chǎng)商： Texas Instruments, Inc.
英文描述： Single-Supply Analog Interface Circuit
中文描述： 單電源模擬接口電路
文件頁(yè)數(shù)： 20/84頁(yè)
文件大?。?/td> 447K
代理商： TLC320AC02I
2–5
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Register Read Data or All 0s
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ADC Conversion Result
DAC Input Data
Control and Device Parameter
Data
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(secondary
communication)
SCLK
FS
DOUT
DIN
[ (B register)/2] FCLK Periods
The time between the primary and secondary frame sync is the time equal to filter clock (FCLK) period multiplied by the
B-register contents divided by two. The time interval is rounded to the nearest shift clock. The secondary frame-sync
signal goes from high to low on the next shift clock low-to-high transition after (B register/2) filter clock periods.
Figure 2–1. Functional Sequence for Primary and Secondary Communication
2.7
The maximum number of slaves is determined by the sum of the individual device delays from the
frame-sync (FS) input low to the frame-sync delayed (FSD) low for all slaves according to equation 1:
Number of Slaves
(n) / tp(FS–FSD) < 1/2 shift-clock period
(1)
Where:
n is the number of slave devices.
Example:
From equation 1 above, the number of slaves is given by equation 2:
1
(n)
1
tp(FS
FSD)
(2)
assuming the master clock is 10.368 MHz and the shift clock is 2.5965 MHz and tp(FS – FSD) is 40 ns, then
according to equation 3, the number of slaves is:
2.5965 MHzx1
40 ns
192
n
2x
1
1000
4.8
(3)
The maximum number of slaves under these conditions is four.
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