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參數(shù)資料
| 型號： | TIBPAL16L8-7MJ |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | HIGH-PERFORMANCE IMPACT-X E PAL CIRCUITS |
| 中文描述： | 高性能影響組E PAL制式電路 |
| 文件頁數(shù)： | 23/30頁 |
| 文件大?。?/td> | 295K |
| 代理商： | TIBPAL16L8-7MJ |
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TIBPAL16R4-5C, TIBPAL16R6-5C, TIBPAL16R8-5C
HIGH-PERFORMANCE
IMPACT-X
PAL
CIRCUITS
SRPS011D – D3359, OCTOBER 1989 – REVISED SEPTEMBER 1992
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
23
metastable characteristics of TIBPAL16R4-5C, TIBPAL16R6-5C, and TIBPAL16R8-5C
At some point a system designer is faced with the problem of synchronizing two digital signals operating at two
different frequencies. This problem is typically overcome by synchronizing one of the signals to the local clock
through use of a flip-flop. However, this solution presents an awkward dilemma since the setup and hold time
specifications associated with the flip-flop are sure to be violated. The metastable characteristics of the flip-flop
can influence overall system reliability.
Whenever the setup and hold times of a flip-flop are violated, its output response becomes uncertain and is said
to be in the metastable state if the output hangs up in the region between V
IL
and V
IH
. This metastable condition
lasts until the flip-flop falls into one of its two stable states, which takes longer than the specified maximum
propagation delay time (CLK to Q max).
From a system engineering standpoint, a designer cannot use the specified data sheet maximum for
propagation delay time when using the flip-flop as a data synchronizer – how long to wait after the specified data
sheet maximum must be known before using the data in order to guarantee reliable system operation.
The circuit shown in Figure 9 can be used to evaluate MTBF (Mean Time Between Failure) and
t for a selected
flip-flop. Whenever the Q output of the DUT is between 0.8 V and 2 V, the comparators are in opposite states.
When the Q output of the DUT is higher than 2 V or lower than 0.8 V, the comparators are at the same logic level.
The outputs of the two comparators are sampled a selected time (
t) after system clock (SCLK). The exclusive
OR gate detects the occurrence of a failure and increments the failure counter.
C1
C1
+
1D
1D
C1
C1
1D
VIH
Comparator
VIL
Comparator
Noise
Generator
DUT
MTBF
Counter
1D
Data in
SCLK
SCLK +
t
Figure 9. Metastable Evaluation Test Circuit
In order to maximize the possibility of forcing the DUT into a metastable state, the input data signal is applied
so that it always violates the setup and hold time. This condition is illustrated in the timing diagram in Figure 10.
Any other relationship of SCLK to data will provide less chance for the device to enter into the metastable state.
t
t
SCLK +
t
trec =
t – CLK to Q (max)
MTBF
Time (sec)
# Failures
Data in
SCLK
Figure 10. Timing Diagram
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TIBPAL16R6-5CJ | HIGH-PERFORMANCE IMPACT-X E PAL CIRCUITS |
| TIBPAL16R6-7M | HIGH-PERFORMANCE IMPACT-X E PAL CIRCUITS |
| TIBPAL16R6-7MFK | HIGH-PERFORMANCE IMPACT-X E PAL CIRCUITS |
| TIBPAL16R6-7MJ | HIGH-PERFORMANCE IMPACT-X E PAL CIRCUITS |
| TIL189-2 | OPTOCOUPLERS/OPTOISOLATORS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TIBPAL16L8AMFK | 制造商:Texas Instruments 功能描述: |
| TIBPAL16LH-25CN | 制造商:Texas Instruments 功能描述: |
| TIBPAL16R4-10C | 制造商:TI 制造商全稱:Texas Instruments 功能描述:HIGH-PERFORMANCE IMPACT-X E PAL CIRCUITS |
| TIBPAL16R410CFN | 制造商:TI 功能描述:* |
| TIBPAL16R4-10CFN | 功能描述:SPLD - 簡單可編程邏輯器件 High-Performance Impact-X PAL Circuit RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
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