參數(shù)資料
型號(hào): TIBPAL16L8-7MJ
廠商: Texas Instruments, Inc.
英文描述: HIGH-PERFORMANCE IMPACT-X E PAL CIRCUITS
中文描述: 高性能影響組E PAL制式電路
文件頁(yè)數(shù): 18/30頁(yè)
文件大小: 295K
代理商: TIBPAL16L8-7MJ
TIBPAL16R4-5C, TIBPAL16R6-5C, TIBPAL16R8-5C
TIBPAL16R4-7M TIBPAL16R6-7M TIBPAL16R8-7M
HIGH-PERFORMANCE
IMPACT-X
PAL
CIRCUITS
SRPS011D – D3359, OCTOBER 1989 – REVISED SEPTEMBER 1992
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
18
f
max
SPECIFICATIONS
f
max
without feedback (see Figure 3)
In this mode, data is presented at the input to the flip-flop and clocked through to the Q output with no feedback.
Under this condition, the clock period is limited by the sum of the data setup time and the data hold time (t
su
+ t
h
).
However, the minimum fmax is determined by the minimum clock period (t
w
high + t
w
low).
Thus, fmaxwithout feedback
(twhigh
1
twlow) or
1
(tsu
th).
CLK
Logic
Array
tsu + th
or
tw high + tw low
C1
1D
Figure 3. f
max
Without Feedback
f
max
with internal feedback (see Figure 4)
This configuration is most popular in counters and on-chip state-machine designs. The flip-flop inputs are
defined by the device inputs and flip-flop outputs. Under this condition, the period is limited by the internal delay
from the flip-flop outputs through the internal feedback and logic array to the inputs of the next flip-flop.
Thus, fmaxwith internal feedback
1
(tsu
tpdCLK
to
FB).
Where tpd CLK-to-FB is the deduced value of the delay from CLK to the input of the logic array.
CLK
Logic
Array
tsu
tpd CLK-to-FB
C1
1D
Figure 4. f
max
With Internal Feedback
相關(guān)PDF資料
PDF描述
TIBPAL16R6-5CJ HIGH-PERFORMANCE IMPACT-X E PAL CIRCUITS
TIBPAL16R6-7M HIGH-PERFORMANCE IMPACT-X E PAL CIRCUITS
TIBPAL16R6-7MFK HIGH-PERFORMANCE IMPACT-X E PAL CIRCUITS
TIBPAL16R6-7MJ HIGH-PERFORMANCE IMPACT-X E PAL CIRCUITS
TIL189-2 OPTOCOUPLERS/OPTOISOLATORS
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