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參數(shù)資料
| 型號： | TFP6424PAP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, THERMALLY ENHANCED, POWER, PLASTIC, TQFP-64 |
| 文件頁數(shù)： | 9/65頁 |
| 文件大小： | 813K |
| 代理商： | TFP6424PAP |
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TFP6422, TFP6424
PanelBus
DIGITAL TRANSMITTER/VIDEO ENCODER COMBO
SLDS118 – MARCH 2000
17
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
clock generation (continued)
The frequencies of CLKENC and CLKOUT are controlled by PLL_X registers and PLL_Y registers, respectively.
They must be related to each other, to other parameters and register values, in a precise manner for correct
video encoding operations. The following equations describe their relationship.
CLKENC = 2*LLEN * Fh
CLKOUT = S*((FLENS+1)/(FLEN+1))*CLKENC
Where
LLEN
= Number of pixels in a scan line
FLENS+1 = Number of lines in the input frame
FLEN+1
= Number of lines in the output frame
Fh
= Line Frequency
S is an integer scaling factor that relates the frequencies between CLKIN and CLKOUT by CLKIN =
CLKOUT/S. S accounts for the frequency divider used by the external device to divide CLKOUT to generate
CLKIN. S takes on the value of 1 or 2.
Refer to the description of PLL_X registers and PLL_Y registers for the procedure to compute the values of
PLL_X registers and PLL_Y registers to satisfy the relationship described above.
When TFP6422/6424 is in DVI or progressive RGB video output mode, similar to the case of TV video output
modes, differential or single–ended CLKIN is used to clock the pixel data and control signals to TFP6422/6424.
However, as opposed to TV video output modes, which use the clock signal on XTALI and XTAL0 as the
reference, TFP6422/6424 uses CLKIN signal to generate the required clock for DVI and progressive RGB video
output. The on–chip PLL takes CLKIN as the reference and generates the 10X clock. This clock is used
internally by the DVI encoder to encode and clock out the DVI bit stream as well as to output TXC+ and TXC–
differential clock along with the DVI data signals.
CLK_CTRL register provides additional control over the clock signals. CLKENCSE bit allows the internal video
encoding clock CLKENC to bypass the PLL and connect directly to CLKIN. DKEN and CLKINDSK[2:0] allow
the user to compensate the skew between CLKIN and the pixel data and control signals. Refer to the description
of CLK_CTRL for details.
timing synchronization
When TFP6422/6424 is in TV video output modes, Video Encoder maintains a set of counters as an internal
time reference to schedule various video encoding processes to take place, which include active video insertion,
color burst insertion, horizontal sync and vertical sync pulse generation. The horizontal counters keep track of
the current horizontal time base in terms of half pixels. The vertical counters maintain vertical time based in
terms of half line. The field counters manage the field sequence. All the counters must be synchronized to the
input video data and control signals for correct operation.
The synchronization is achieved by resetting the counters at the periodical synchronization events. Use
HTRIGGER registers and VTRIGGER registers to program the values that the counters are reset to. These
registers can be used to define the horizontal phase and vertical phase relationship between the input image
and the output image.
When the input digital video is in interlace mode with embedded synchronization (FMT[3:0] = 1100 or 1101),
the ‘F’ bit in the SAV and EAV codes is used to synchronize the vertical counter and the field counter, and the
‘H’ bit is used to synchronize the horizontal counter. At the ‘0’ to ‘1’ transition of ‘F’ bit, the field counter is reset
to indicate EVEN field (second field) and the vertical counter is reset to the value defined in the VTRIGGER
registers. At the ‘0’ to ‘1’ transition of ‘H’ bit, the horizontal counter is reset to the values defined in the
HTRIGGER registers.
PRODUCT
PREVIEW
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