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參數(shù)資料
| 型號： | TFP6424PAP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, THERMALLY ENHANCED, POWER, PLASTIC, TQFP-64 |
| 文件頁數(shù)： | 10/65頁 |
| 文件大?。?/td> | 813K |
| 代理商： | TFP6424PAP |
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TFP6422, TFP6424
PanelBus
DIGITAL TRANSMITTER/VIDEO ENCODER COMBO
SLDS118 – MARCH 2000
18
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing synchronization (continued)
When the input digital video is in interlace mode with external synchronization (FMT[3:0] = 1000 or 1001), the
rising edge of the VSYNC resets the vertical counter and the rising edge of HSYNC resets the horizontal counter.
The field counter in this case is free–running and does not reset. However, the FID pin outputs the current field
ID(EVEN or ODD).
When the input digital video is in progressive mode with external sync, the Scaling Processor performs the
scaling and the video port clock (CLKIN0 and CLKIN1) runs at a different frequency than the internal video
encoding clock (CLKENC). As a result, the digital video input timing is somewhat decoupled from the internal
video encoder timing. In this case, VSYNC (in the CLKIN domain) resets both the vertical counter and the
horizontal counter (in CLKENC domain). Special precaution is taken in the synchronization logic to handle the
potential metastability caused by a signal travelling across two different clock domains. The field counter does
not reset and runs freely. The FID pin outputs the current field ID (EVEN or ODD).
When the input digital video is in progressive mode with embedded sync, the ‘0’ to ‘1’ transition of ‘V’ bit resets
the vertical counter and the ‘0’ to ‘1’ transition of ‘H’ bit resets the horizontal counter. The field counter does not
reset and runs freely. The FID pin outputs the current filed ID (EVEN or ODD).
The timing synchronization described above is not applicable when TFP6422/6424 is in DVI output or
progressive RGB output mode.
As mentioned previously, when the Scaling Processor is enabled (TV video output mode and progressive digital
video input), the time base of Video Encoder core is decoupled from the timing of the Video Port. A FIFO is
placed between two domains to transfer the pixels across two domains. Video Encoder in this case acts as a
master that sources the pixel data from the FIFO. The point of time at each output scan line when Video Encoder
begins to request data is critical. It must be properly chosen not to overflow the FIFO. The point of time when
each output scan line starts to request pixel data is controlled by BPIX registers. To avoid overflowing the FIFO,
the HTRIGGER registers must be adjusted based on the value in BPIX.
See the descriptions of HTRIGGER, VTRIGGER and BPIX for details.
hot plug/unplug (auto connect/disconnect detection)
TFP6422/6424 supports Hot Plug/Unplug (auto connect/disconnect detection) for DVI link as well as the analog
video connections. The connection status of DVI link, HOTPLUG sense pin and DACs output, is provided by
the CON_STATUS register. RXCON bit indicates if a DVI receiver is connected to the TXC+ and TXC–. HPCON
bit reflects the current state of the HTPLUG pin connected to the monitor via DVI connector. HTPLUG pin is 5V
tolerant with an internal digital debouncing circuit to allow for direct connection to the DVI connector.
DACCON[0:3] bits reflect the connection status on the output of the DACs on CVBS, Y/G, C/R/Pr and B/Pr pins.
Whenever one or more connection status bits change states, the corresponding bit in the IN_STATUS bit is to
‘1’ to record the changes. An interrupt can also be generated as an option. The interrupt for each type of
connect/disconnect event can be individually enabled or disabled by writing a ‘1’ or ‘0’ to the corresponding bit
in the INT_ENABLE register. Notice that INT_ENABLE register does not affect the state of the INT_STATUS
bits. A host can either poll the INT_STATUS bits or rely on the interrupt to learn about the states or the change
of states of the connections. The interrupt continues to be asserted until ‘1’ is written to the corresponding
interrupt bit in the INT_STATUS register to reset the bit back to ‘0’. Writing ‘0’ to an interrupt status bit has no
effect.
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