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參數(shù)資料
| 型號： | TFP6424PAP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, THERMALLY ENHANCED, POWER, PLASTIC, TQFP-64 |
| 文件頁數(shù)： | 4/65頁 |
| 文件大?。?/td> | 813K |
| 代理商： | TFP6424PAP |
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TFP6422, TFP6424
PanelBus
DIGITAL TRANSMITTER/VIDEO ENCODER COMBO
SLDS118 – MARCH 2000
12
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
I2C interface (continued)
The basic access cycle consists of the following:
D A start condition
D A slave address cycle
D A subaddress cycle
D Any number of data cycles
D A stop condition
The start and stop conditions are shown in Figure 2. The high to low transition of SDA while SCL is high defines
the start condition. The low to high transition of SDA while SCL is high defines the stop condition. Each cycle,
data or address, consists of 8 bits of serial data followed by one acknowledge bit generated by the receiving
device. Thus, each data/address cycle contains 9 bits as shown in Figure 2.
SCL
1
2
3
4
5
6
7
8
9
SCL
SDA
1
2
3
4
5
6
7
8
9
2
3
4
5
6
7
1
Slave Address
MSB
Sub Address
Data
Stop
Figure 2. I2C Access Cycles
Following a start condition, each I2C device decodes the slave address. The TFP6422 and TFP6424 responds
with an acknowledge by pulling the SDA line low during the ninth clock cycle if it decodes the address as its
address. During subsequent subaddress and data cycles the TFP6422 and TFP6424 responds with
acknowledge as shown in Figure 3. The subaddress is auto-incremented after each data cycle.
The transmitting device must not drive the SDA signal during the acknowledge cycle so that the receiving device
may drive the SDA signal low. The not acknowledge, A, condition is indicated by the master by keeping the SDA
signal high just before it asserts the stop, P, condition. This sequence terminates a read cycle as shown in
Figure 4.
The slave address consists of 7 bits of address along with 1 bit of read/write information as shown below in
Figures 3 and 4. For the TFP6422 and TFP6424, the possible slave addresses (including the r/w bit) are 0x40,
0x42 for write cycles and 0x41 and 0x43 for read cycles. Refer to register description, for additional base
address information.
S
Slave Address
W
Sub Address
A
Data
A
Data
A
P
From Transmitter
From Receiver
/
Not Acknowledge (SDA A High)
A
Acknowledge
S
Start Condition
P
Stop Condition
Figure 3. I2C Write Cycle
PRODUCT
PREVIEW
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