參數(shù)資料
型號： TFP513PAPG4
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝： 10 X 10 MM, 1.00 MM HEIGHT, 0.50 MM PITCH, HTQFP-64
文件頁數(shù)： 23/32頁
文件大?。?/td> 1206K
代理商： TFP513PAPG4
TFP513
TI PanelBus DIGITAL TRANSMITTER
SLLS611 AUGUST 2004
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
functional block diagram
12-/24-Bit
I/F
Data
Format
Universal Input
T.M.D.S. Transmitter
Serializer
Control
I2C Slave I/F
For DDC
1.8-V Regulators
With Bypass
Capacitors
PLL
TX2
±
TX1
±
TX0
±
TXC
±
TFADJ
IDCK
±
DATA[23:0]
DE
VSYNC
HSYNC
EDGE/HTPLG
MSEN
PD
ISEL/RST
BSEL/SCL
DSEL/SDA
VREF
Encoder
HDCP
Cipher
HDCP
Encryption
RDA
RCL
Encrypted
Embedded
HDCP Keys
Key Decryption
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NUMBER
I/O
DESCRIPTION
Input Pins
DATA[23:12]
3647
I
The upper 12 bits of the 24-bit pixel bus.
In 24-bit, single-edge input mode (BSEL = high), this bus inputs the top half of the 24-bit pixel bus.
In 12-bit, dual-edge input mode (BSEL = low), these bits do not input pixel data. In this mode, the state of
DATA[23:16] is input to the I2C register CFG. This allows 8 bits of user configuration data to be read by
the graphics controller through the I2C interface (see the I2C register descriptions section).
Note: All unused data inputs must be tied to GND or VDD.
DATA[11:0]
5055,
5863
I
The lower 12 bits of the 24-bit pixel bus/12-bit pixel bus input.
In 24-bit, single-edge input mode (BSEL = high), this bus inputs the bottom half of the 24-bit pixel bus.
In 12-bit, dual-edge input mode (BSEL = low), this bus inputs 1/2 pixel (12 bits) at every latch edge (both
rising and falling) of the clock.
DE
2
I
Data enable. As defined in the DVI 1.0 specification, the DE signal allows the transmitter to encode pixel
data or control data on any given input clock cycle. During active video (DE = high), the transmitter
encodes pixel data, DATA[23:0]. During the blanking interval (DE = low), the transmitter encodes
HSYNC, VSYNC, and CTL[3:1].
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