參數(shù)資料
型號(hào)： TFP510PAPG4
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝： 10 X 10 MM, 1 MM HEIGHT, 0.50 MM PITCH, GREEN, PLASTIC, HTQFP-64
文件頁(yè)數(shù)： 23/27頁(yè)
文件大?。?/td> 383K
代理商： TFP510PAPG4
TFP510
TI PanelBus DIGITAL TRANSMITTER
SLDS146B JANUARY 2002 REVISED DECEMBER 2002
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
Configuration/Programming Pins (Continued)
MSEN
11
O
Monitor sense/programmable output 1. The operation of this pin depends on whether the I2C interface is
enabled or disabled. This pin has an open-drain output and is only 3.3-V tolerant. An external 5-k
pullup resistor connected to VDD is required on this pin.
When I2C is disabled (ISEL = low), a low level indicates a powered on receiver is detected at the
differential outputs. A high level indicates a powered-on receiver is not detected. This function is valid
only in dc-coupled systems.
When I2C is enabled (ISEL = high), this output is programmable through the I2C interface (see the I2C
register descriptions).
PD
10
I
Power down (active low). In the power-down state only the digital I/O buffers and I2C interface remain
active.
When I2C is disabled (ISEL = low), a high level selects the normal operating mode. A low level selects
the power-down mode.
When I2C is enabled (ISEL = high), the power-down state is selected through I2C. In this configuration,
the PD pin should be tied to GND.
Note: The default register value for PD is low, so the device is in power-down mode when I2C is first
enabled or after an I2C RESET.
VREF
3
I
Input reference voltage. Selects the swing range of the digital data inputs (DATA[23:0], DE, HSYNC,
VSYNC, and IDCK
±).
For high-swing 3.3-V input signal levels, VREF should be tied to VDD.
For low-swing input signal levels, VREF should be set to half of the maximum input voltage level. See the
recommended operating conditions section for the allowable range for VREF.
The desired VREF voltage level is typically derived using a simple voltage divider circuit.
Reserved
NC
49
I
No connection required. If connected, tie high.
RESERVED
34, 35
I
These pins are reserved and must be tied to GND for normal operation.
DVI Differential Signal Output Pins
TFADJ
19
I
Full-scale adjust. This pin controls the amplitude of the DVI output voltage swing, determined by the
value of the pullup resistor RTFADJ connected to TVDD.
TX0+
TX0
25
24
O
Channel-0 DVI differential output pair. TX0
± transmits the 8-bit blue pixel data during active video and
HSYNC and VSYNC during the blanking interval.
TX1+
TX1
28
27
O
Channel-1 DVI differential output pair. TX1
± transmits the 8-bit green pixel data during active video and
CTL[1] during the blanking interval.
TX2+
TX2
31
30
O
Channel-2 DVI differential output pair. TX2
± transmits the 8-bit red pixel data during active video and
CTL[3:2] during the blanking interval.
TXC+
TXC
22
21
O
DVI differential output clock.
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