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參數(shù)資料
| 型號： | TFP510PAPG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1 MM HEIGHT, 0.50 MM PITCH, GREEN, PLASTIC, HTQFP-64 |
| 文件頁數(shù)： | 22/27頁 |
| 文件大?。?/td> | 383K |
| 代理商： | TFP510PAPG4 |
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TFP510
TI PanelBus DIGITAL TRANSMITTER
SLDS146B JANUARY 2002 REVISED DECEMBER 2002
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
Input Pins (Continued)
DK3
MDA/DK2
MCL/DK1
6
7
8
I/O
The operation of these three multifunction inputs depends on the setting of the ISEL (pin 13) input. All
three inputs support 3.3-V CMOS signal levels and contain weak pulldown resistors so that if left
unconnected they default to all low.
When the I2C bus is disabled (ISEL = low), then these three inputs become the de-skew inputs, DK[3:1],
used to adjust the setup and hold times of the pixel data inputs, DATA[23:0], relative to the clock input,
IDCK
±.
When the I2C bus is enabled (ISEL = high), MDA and MCL are open-drain I/O pins used for the I2C
interface to the key EEPROM, which can be used by the HDCP. In this case, MCL is the memory clock
signal, while MDA is the memory data signal. The DK3 pin is not used in this mode. Pins 78 require a
5-k
resistor connected to VDD when used for EEPROM I2C interface.
HSYNC
4
I
Horizontal sync input
IDCK
IDCK+
56
57
I
Differential clock input. The TFP510 supports both single-ended and fully differential clock input modes.
In the single-ended clock input mode, the IDCK+ input (pin 57) should be connected to the single-ended
clock source and the IDCK input (pin 56) should be tied to GND. In the differential clock input mode, the
TFP510 uses the crossover point between the IDCK+ and IDCK signals as the timing reference for
latching incoming data DATA[23:0], DE, HSYNC, and VSYNC. The differential clock input mode is only
available in the low-signal-swing mode.
VSYNC
5
I
Vertical sync input
Configuration/Programming Pins
BSEL/SCL
15
I/O
Input bus select / I2C clock input. The operation of this pin depends on whether the I2C interface is
enabled or disabled. This pin is only 3.3-V tolerant.
When I2C is disabled (ISEL = low), a high level selects 24-bit input, single-edge input mode. A low level
selects 12-bit input, dual-edge input mode.
When I2C is enabled (ISEL = high), this pin functions as the I2C clock input (see the I2C register
descriptions section). In this configuration, this pin has an open-drain output that requires an external
5-k
pullup resistor connected to VDD.
DSEL/SDA
14
I/O
DSEL/I2C data. The operation of this pin depends on whether the I2C interface is enabled or disabled.
This pin is only 3.3-V tolerant.
When I2C is disabled (ISEL = low), this pin is used with BSEL and VREF to select the single-ended or
differential input clock mode (see the universal graphics controller interface modes section).
When I2C is enabled (ISEL = high), this pin functions as the I2C bidirectional data line. In this
configuration, this pin has an open-drain output that requires an external 5-k
pullup resistor connected
to VDD.
EDGE/HTPLG
9
I
Edge select/hot plug input. The operation of this pin depends on whether the I2C interface is enabled or
disabled. This input is 3.3-V tolerant only.
When I2C is disabled (ISEL = low), a high level selects the primary latch to occur on the rising edge of the
input clock IDCK+. A low level selects the primary latch to occur on the falling edge of the input clock
IDCK+. This is the case for both single-ended and differential input clock modes.
When I2C is enabled (ISEL = high), this pin is used to monitor the hot plug detect signal (see the DVI or
VESA
P&D and DFP standards). When used for hot-plug detection, this pin requires a series 1-k
resistor.
ISEL/RST
13
I
I2C interface select / I2C RESET (active low, asynchronous).
If ISEL is high, then the I2C interface is active. Default values for the I2C registers can be found in the I2C
register descriptions section.
If ISEL is low, then I2C is disabled and the chip configuration is specified by the configuration pins
(BSEL, DSEL, EDGE, VREF) and state pins (PD, DKEN).
If ISEL is brought low and then back high, the I2C state machine is reset. The register values are
changed to their default values and are not preserved from before the reset.
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