參數(shù)資料
型號: TEA5764UK
廠商: NXP SEMICONDUCTORS
元件分類: 接收器
英文描述: FM radio + RDS
中文描述: FM, AUDIO SINGLE CHIP RECEIVER, PBGA34
封裝: 4 X 4 MM, WLB-34
文件頁數(shù): 22/64頁
文件大?。?/td> 287K
代理商: TEA5764UK
TEA5764HN_2
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 9 August 2005
22 of 64
Philips Semiconductors
TEA5764HN
FM radio + RDS
In
Equation 6
, the pause detector has measured 1
×
16 ms ‘pause’, 8
×
1.5 ms ‘no pause’
and 1
×
16 ms pause. Therefore on average the pause detector has measured 16 ms
12
ms + 16 ms = 20 ms pause time and hence a pause will be detected.
The PSCOn signal goes directly to the software port. The PDFLAG is set by the integrator
and goes to the bus. The interrupt line is triggered by the PDFLAG.
9.1.4.7
Frequency ready flag
The frequency ready flag bit is set to logic 1 when the automatic tuning has finished a
search, a preset or an RDS AF update. This bit is described in
Table 4
and
Table 5
. The
FRRFLAG is cleared by a read of byte1R.
t
np(min)
> 5 ms.
(1) The reference level is defined in kHz, but is internally transformed to mV e.g. 22.5 kHz = 75 mV; 1 kHz = 3.3 mV.
(2) The actual PSCO signal behaves as shown in the top diagram, in the bottom diagram it is assumed that all samples are
taken at peaks of the audio signal resulting in PSCOn.
Fig 7.
Operation and timing of pause detection according to levels set in
Table 38
001aac795
audio signal
PSCO
audio
0
(2)
no audio present
audio present
PT x 2341
+ reference level "PL" [mV] (1)
pause
no pause
reference level "PL"
0
PSCOn
t
pause
t
audio
t
pause
PDFLAG
integrator
output
t
1
t
2
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