參數(shù)資料
型號(hào)： TEA5764UK
廠商： NXP SEMICONDUCTORS
元件分類： 接收器
英文描述： FM radio + RDS
中文描述： FM, AUDIO SINGLE CHIP RECEIVER, PBGA34
封裝： 4 X 4 MM, WLB-34
文件頁(yè)數(shù)： 21/64頁(yè)
文件大?。?/td> 287K
代理商： TEA5764UK
TEA5764HN_2
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 9 August 2005
21 of 64
Philips Semiconductors
TEA5764HN
FM radio + RDS
2. After a search, a preset or an AF update, the threshold for comparison is switched to
the hysteresis level. The hysteresis level is set by the combination of bits SSL[1:0] and
bit LHSW; see
Table 24
. The result is a hysteresis as shown in
Table 26
. Then the
ADC level starts to run automatically and compares the level every 500
μ
s with the
hysteresis level. Bit LEVFLAG is set if the RSSI level drops below the threshold level
set by bits SSL[1:0] in combination with bit LHSW (see
Table 26
); the hardware
interrupt is only generated if the corresponding mask bit is set. Bit LHSW allows either
a small or a large hysteresis to be selected which results in the levels of the left RSSI
hysteresis threshold column for bit LHSW = 0 and the right RSSI hysteresis threshold
column; see
Table 26
. When a search or preset is done with the ADC level set to 3
then when the algorithm has finished, the threshold level is set to 0. Hence the
LEVFLAG will never be set.
Bit LEVFLAG is cleared by a read of the INTMSK byte1R, or by starting the tuning
algorithm.
9.1.4.6
Pause detection flag
The pause detector monitors the amplitude of the audio signal and starts counting if it
drops below the reference level. When the counter reaches the specified count time, a
pause is detected and the PDFLAG is set and will generate an interrupt if bit PDMSK is
set to logic 1. The PDFLAG operates independently of bit PDMSK and is only active when
the RDS decoder is switched on when bit PUPD is set to logic 1 and when the RDS
decoder is not idle if synchronization is lost.
See
Figure 7
. When the peak audio level of the (L+R) drops below the threshold level at t
1
it counts the duration of the pause. If the pause lasts longer than the value set by the PT
bits, bit PDFLAG is set which in turn generates a hardware interrupt (bit PDMSK set to
logic 1). The threshold level at t
1
is set by the PL bits shown in
Table 38
.
Bit PDFLAG is cleared by a read of byte1R on condition that the read action occurs more
than 500
μ
s after receiving the pause interrupt on the INTX line.
The circuit should ignore short transients where the audio level momentarily rises above
the threshold (at t
2
).
A pause is detected by comparing the amplitude of the audio signal with the reference
level selected by the PL bits. The resultant signal PSCO produced by this comparison is
sampled at a frequency of 2341 Hz resulting in signal PSCOn. A pause is detected under
the conditions given by
Equation 4
and
Equation 5
.
(4)
(5)
where N is the number of samples taken over time and PT is the pause time selected by
bus bits PT. When a pause is detected, the integrator will be reset. The integrator value
cannot be less than zero; therefore if in
Equation 4
, the value of the second SUM
becomes larger than the first SUM, the output of the integrator remains at zero.
Suppose that PT = 20 ms, t
pause
= 16 ms and t
audio
= 1.5 ms. The pause detector will
count according to
Equation 5
as shown in
Equation 6
:
(6)
SUM 0toN
1
–
)
PSCOn
[
0
=
]
8
SUM 0toN
1
–
)
×
PSCOn
1
=
[
]
–
{
}
PT
2341
×
>
t
pause
8
t
audio
PT
>
×
–
2
t
pause
8
t
×
–
audio
×
20 ms
2
16 ms
8
1.5 ms
×
–
×
≥
20 ms
=
=
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TEA5766UK/N1,023 功能描述:調(diào)節(jié)器/解調(diào)器 FM RADIO + RDS RoHS:否 制造商:Texas Instruments 封裝 / 箱體:PVQFN-N24 封裝:Reel
TEA5766UK/N1,118 功能描述:調(diào)節(jié)器/解調(diào)器 FM RADIO + RDS RoHS:否 制造商:Texas Instruments 封裝 / 箱體:PVQFN-N24 封裝:Reel
TEA5766UK/N1/S21,0 功能描述:調(diào)諧器 FM RADIO + RDS RoHS:否 制造商:NXP Semiconductors 功能: 噪聲系數(shù): 工作電源電壓: 最小工作溫度: 最大工作溫度:
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