參數(shù)資料
型號(hào)： TDA9910
廠商： NXP Semiconductors N.V.
元件分類： ADC
英文描述： 12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC) direct/ultra high IF sampling
中文描述： 12位，高達(dá)80 Msample /秒，模擬到數(shù)字轉(zhuǎn)換器（ADC）直接/超高IF采樣
文件頁(yè)數(shù)： 9/21頁(yè)
文件大小： 138K
代理商： TDA9910
9397 750 14418
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Objective data sheet
Rev. 02 — 9 December 2004
9 of 21
Philips Semiconductors
TDA9910
12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC)
[1]
D = guaranteed by design;
C = guaranteed by characterization;
I = 100 % industrially tested.
[2]
The circuit has two clock inputs: CLK and CLKN. There are 5 modes of operation:
a) PECL mode 1: (DC levels vary 1:1 with V
CCD
) CLK and CLKN inputs are at differential PECL levels.
b) PECL mode 2: (DC levels vary 1:1 with V
CCD
) CLK input is at PECL level and sampling is taken on the falling edge of the clock input
signal. A DC level of 3.65 V has to be applied on CLKN decoupled to GND via a 100 nF capacitor.
c) PECL mode 3: (DC levels vary 1:1 with V
CCD
) CLKN input is at PECL level and sampling is taken on the rising edge of the clock input
signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF capacitor.
d) Differential AC driving mode 4: When driving the CLK input directly and with any AC signal of minimum 1 V (p-p) and with a DC level
of 2.5 V, the sampling takes place at the falling edge of the clock signal.
When driving the CLKN input with the same signal, sampling takes place at the rising edge of the clock signal. It is recommended to
decouple the CLKN or CLK input to DGND via a 100 nF capacitor.
e) TTL mode 5: CLK input is at TTL level and sampling is taken on the falling edge of the clock input signal.
In that case CLKN pin has to be connected to the ground.
[3]
The ADC input range can be adjusted with an external reference connected to FSIN pin. This voltage has to be referenced to V
CCA.
Output data acquisition: the output data is available after the maximum delay of t
d(o)
.
The
3 dB analog bandwidth is determined by the 3 dB reduction in the reconstructed output, the input being a full-scale sine wave.
[4]
[5]
[6]
The total harmonic distortion is obtained with the addition of the first five harmonics.
[7]
The signal-to-noise ratio takes into account all harmonics above five and noise up to Nyquist frequency.
SFDR
spurious free dynamic
range TDA9910/6
f
i
= 21.4 MHz
f
i
= 93 MHz
f
i
= 175 MHz
f
i
= 21.4 MHz
f
i
= 93 MHz
f
i
= 175 MHz
f
i
= 93 MHz; 5 MHz
channel spacing;
B = 4.096 MHz
f
i
= 175 MHz; 5 MHz
channel spacing;
B = 4.096 MHz
f
i1
= 21 MHz;
f
i2
= 22 MHz
f
i1
= 93 MHz;
f
i2
= 96 MHz
f
i1
= 174 MHz;
f
i2
= 176 MHz
f
i1
= 21 MHz;
f
i2
= 22 MHz
f
i1
= 93 MHz;
f
i2
= 96 MHz
f
i1
= 174 MHz;
f
i2
= 176 MHz
-
-
-
-
-
-
-
76
73
73
79
75
72
86
-
-
-
-
-
-
-
dBc
dBc
dBc
dBc
dBc
dBc
dB
spurious free dynamic
range TDA9910/8
ACPR
adjacent channel power
rejection
-
74
-
dB
d2
(IM2)
second order
intermodulation
distortion
[8]
-
81
-
dBFS
-
83
-
dBFS
-
80
-
dBFS
d3
(IM3)
third order
intermodulation
distortion
[8]
-
87
-
dBFS
-
88
-
dBFS
-
83
-
dBFS
Table 5:
V
CCA
= 4.75 V to 5.25 V; V
CCD
= 4.75 V to 5.25 V; V
CCO
= 2.7 V to 3.6 V; AGND and DGND shorted together; T
amb
=
40
°
C
to +85
°
C; V
IN(p-p)
V
INN(p-p)
= 2.0 V
0.5 dB; V
FSIN
= V
CCA1
1.77 V; V
i(CM)
= V
CCA1
1.85 V; typical values measured at
V
CCA
= V
CCD
= 5 V, V
CCO
= 3.3 V T
amb
= 25
°
C and C
L
= 10 pF; unless otherwise specified.
Symbol Parameter
Conditions
Characteristics
…continued
Test
[1]
Min
Typ
Max
Unit
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