參數(shù)資料
型號: TDA9910
廠商: NXP Semiconductors N.V.
元件分類: ADC
英文描述: 12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC) direct/ultra high IF sampling
中文描述: 12位,高達(dá)80 Msample /秒,模擬到數(shù)字轉(zhuǎn)換器(ADC)直接/超高IF采樣
文件頁數(shù): 12/21頁
文件大?。?/td> 138K
代理商: TDA9910
9397 750 14418
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Objective data sheet
Rev. 02 — 9 December 2004
12 of 21
Philips Semiconductors
TDA9910
12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC)
The TDA9910 allows to modify the ADC full-scale. This could be done with FSIN
(full-scale input) according to
Figure 5
.
The TDA9910 generates an adjustable clock output called Complete Conversion Signal
(CCS), which can be used to control the acquisition of converted output data by the digital
circuit connected to the TDA9910 output data bus. Two logic inputs, DEL0 and DEL1 pins,
allow to adjust the delay of the edge of the CCS signal to achieve an optimal position in
the stable, usable zone of the data.
10. Definitions
10.1 Static parameters
10.1.1
INL (integral non-linearity)
It is defined as the deviation of the transfer function from a best fit straight line (linear
regression computation). The INL of the code i is obtained from the equation:
where:
S is corresponding to the slope of the ideal straight line (code width); i is corresponding to
the code value.
10.1.2
DNL (differential non-linearity)
It is the deviation in code width from the value of 1 LSB.
Table 8:
DEL1
0
0
1
1
Complete conversion signal selection
DEL0
CCS output
0
high-impedance
1
active, typical delay 0.2 ns
0
active, typical delay 1.3 ns
1
active, typical delay 2.4 ns
(1) t
cd(o)
is referenced to the middle of the active data.
Fig 6.
Complete conversion signal timing diagram.
001aaa516
D0 to D11
(1)
CCS
t
cd(o)
INL i
( )
V
i
( )
-------------------------------------------
V
ideal
(
S
)
=
DNL i
( )
V
i
----------------------------------------
1
+
(
)
V
i
( )
S
=
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