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參數(shù)資料
| 型號(hào)： | TDA9910 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | ADC |
| 英文描述： | 12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC) direct/ultra high IF sampling |
| 中文描述： | 12位，高達(dá)80 Msample /秒，模擬到數(shù)字轉(zhuǎn)換器（ADC）直接/超高IF采樣 |
| 文件頁數(shù)： | 7/21頁 |
| 文件大?。?/td> | 138K |
| 代理商： | TDA9910 |
9397 750 14418
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Objective data sheet
Rev. 02 — 9 December 2004
7 of 21
Philips Semiconductors
TDA9910
12-bit, up to 80 Msample/s, Analog-to-Digital Converter (ADC)
I
IL
I
IH
Digital inputs: pins DEL0 and DEL1
V
IL
LOW-level input voltage
V
IH
HIGH-level input voltage
I
IL
LOW-level input current
I
IH
HIGH-level input current
Voltage controlled regulator output: pin CMADC
V
o(CM)
common mode output
voltage
LOW-level input current
HIGH-level input current
V
IL
= 0.8 V
V
IH
= 2.0 V
-
-
5
5
-
-
μ
A
μ
A
DGND
0.7
×
V
CCD
-
-
-
-
0.3
×
V
CCD
V
CCD
-
-
V
V
μ
A
μ
A
V
IL
= 0.8 V
V
IH
= 2.0 V
80
80
I
L
= 0 mA
I
L
= 2 mA
-
-
V
CCA
1.88 -
V
CCA
1.91 -
V
V
Reference voltage input: pin FSIN
[3]
V
FSIN
full-scale fixed voltage
I
FSIN
input current
V
i(p-p)
input voltage
(peak-to-peak value)
-
-
1.5
V
CCA
1.84 -
1
1.9
V
μ
A
V
-
2.0
see
Figure 5
;
V
i
= V
IN
V
INN
;
V
i(CM)
= V
CCA
1.91 V
Full-scale voltage controlled regulator output: pin FSOUT
V
o(ref)
1.9 V full-scale output
voltage
I
L
= I
FSIN
I
L
= 2 mA
-
-
V
CCA
1.84 -
V
CCA
1.87 -
V
V
Digital outputs: pins D11 to D0, IR and CCS
Output levels
V
OL
LOW-level output voltage
V
OH
HIGH-level output voltage I
OH
=
0.4 mA
I
OZ
output current in 3-state
I
OL
= 2 mA
DGND
V
CCO
0.5 -
20
-
DGND + 0.5
V
CCO
+20
V
V
μ
A
output level between
0.5 V and V
CCO
1
Timing
[4]
t
d(s)
t
h(o)
t
d(o)
3-state output delay
t
dZH
t
dZL
t
dHZ
t
dLZ
Clock timing inputs: pins CLK and CLKN
f
CLK(min)
minimum clock frequency
f
CLK(max)
maximum clock frequency duty cycle 45 % to
sampling delay time
output hold time
output delay time
C
L
= 10 pF
C
L
= 10 pF
C
L
= 10 pF
-
-
-
0.2
4
5
-
-
-
ns
ns
ns
enable HIGH
enable LOW
disable HIGH
disable LOW
-
-
-
-
3
5
8
5
-
-
-
-
ns
ns
ns
ns
-
80
-
-
8
-
Msample/s
Msample/s
65 %
f
i
= 175 MHz
f
i
= 175 MHz
t
CLKH
t
CLKL
clock pulse width HIGH
clock pulse width LOW
5.6
5.6
-
-
-
-
ns
ns
Table 5:
V
CCA
= 4.75 V to 5.25 V; V
CCD
= 4.75 V to 5.25 V; V
CCO
= 2.7 V to 3.6 V; AGND and DGND shorted together; T
amb
=
40
°
C
to +85
°
C; V
IN(p-p)
V
INN(p-p)
= 2.0 V
0.5 dB; V
FSIN
= V
CCA1
1.77 V; V
i(CM)
= V
CCA1
1.85 V; typical values measured at
V
CCA
= V
CCD
= 5 V, V
CCO
= 3.3 V T
amb
= 25
°
C and C
L
= 10 pF; unless otherwise specified.
Symbol Parameter
Conditions
Characteristics
…continued
Test
[1]
Min
Typ
Max
Unit
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