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參數(shù)資料
| 型號： | TDA9321H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | I2C-bus controlled TV input processor |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | PLASTIC, QFP-64 |
| 文件頁數(shù)： | 34/44頁 |
| 文件大小： | 249K |
| 代理商： | TDA9321H |
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1998 Dec 16
34
Philips Semiconductors
Preliminary specification
I
2
C-bus controlled TV input processor
TDA9321H
To prevent the horizontal synchronization being disturbed by anti copy signals such as Macrovision the phase
detector is gated during the vertical retrace period from line 11 to 17 (60 Hz signal) or from line 11 to 22 (50 Hz
signal) so that pulses during scan have no effect on the output voltage. The width of the gate pulse is approximately
22
μ
s. During weak signal conditions (noise detector active) the gating is active during the complete scan period and
the width of the gate pulse is reduced to 5.7
μ
s so that the effect of noise is reduced to a minimum.
The output current of the phase detector in the various conditions is shown in Table 57.
34. The timing pulses for the vertical ramp generator are obtained from the horizontal oscillator via a divider circuit.
This divider circuit has 3 modes of operation:
a) Search mode large window.
This mode is switched on when the circuit is not synchronized or when a non-standard signal [number of lines
per frame outside the range between 311 and 314 (50 Hz mode) or between 261 and 264 (60 Hz mode)] is
received. In the search mode the divider can be triggered between line 244 and line 361 (approximately
43.3 to 64.5 Hz).
b) Standard mode narrow window.
This mode is switched on when more than 15 succeeding vertical sync pulses are detected in the narrow window.
When the circuit is in the standard mode and a vertical sync pulse is missing the retrace of the vertical ramp
generator is started at the end of the window. Consequently, the disturbance of the picture is very small.
The circuit will switch back to the search window when, for 6 successive vertical periods, no sync pulses are
found within the window.
c) Standard TV-norm [divider ratio 525 (60 Hz) or 625 (50 Hz)].
When the system is switched to the narrow window a check is performed to establish whether the incoming
vertical sync pulses are in accordance with the TV-norm. When 15 standard TV-norm pulses are counted the
divider system is switched to the standard divider ratio mode. In this mode the divider is always reset at the
standard value even if the vertical sync pulse is missing.
When 3 vertical sync pulses are missed the system switches back to the narrow window and when also in this
window no sync pulses are found (condition 3 missing pulses) the system switches over to the search window.
The vertical divider needs some waiting time during channel-switching of the tuner. When a fast reaction of the
divider is required during channel-switching the system can be forced to the search window by means of bit NCIN in
subaddress 06.
35. The delay between the positive edge of VA and the positive edge of CLP (
≈
negative edge of HA) after VA is 32.0
μ
s
for field 1 and 0
μ
s for field 2. Especially for PALplus signals the regenerated VA pulses must have a fixed and known
phase relation to the undisturbed VA pulses of the incoming video signal. This relationship must remain correct as
long as the vertical divider is in the standard mode (indirect sync mode). Therefore the coincidence window used
here must be a half line window. With a well defined phase relationship of the generated VA pulses to the generated
HA pulses a correct field identification and all the required timing signals referring to a certain line in each frame can
be generated externally in the PALplus decoder environment.
36. Pins 19 and 22 are for general purpose outputs that can be used to switch external circuits e.g. sound traps, etc.
They are controlled via the I
2
C-bus by bits OS0 (pin 19) and OS1 (pin 22).
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