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參數(shù)資料
| 型號(hào)： | TDA9321H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | I2C-bus controlled TV input processor |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | PLASTIC, QFP-64 |
| 文件頁數(shù)： | 29/44頁 |
| 文件大?。?/td> | 249K |
| 代理商： | TDA9321H |
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1998 Dec 16
29
Philips Semiconductors
Preliminary specification
I
2
C-bus controlled TV input processor
TDA9321H
H
ORIZONTAL OSCILLATOR
f
fr
f
fr
free-running frequency
spread on free-running
frequency
frequency dependency with
respect to the supply voltage
frequency variation with
temperature
15625
±
2
Hz
%
f/
V
P
V
P
= 8.0 V
±
10%; note 6
0.2
0.5
%
f/T
T
amb
= 0 to 70
°
C; note 6
80
Hz
F
IRST CONTROL LOOP
(
PIN
PH1LF); note 33
f
hr(PLL)
f
cr(PLL)
S/N
PLL holding range
PLL catching range
signal-to-noise ratio
±
0.6
15
±
0.9
±
0.9
17
±
1.2
19
kHz
kHz
dB
note 6
for the video input signal
at which the time
constant is switched
hys
sw
σ
H
ORIZONTAL PULSE OUTPUT AND CLAMP PULSE INPUT
/
OUTPUT
(
PIN
HA/CLP)
hysteresis at the switching point
sigma value of phase jitter
2
3
4
5
dB
ns
in automatic mode;
±
3
σ
Switched to HA output (bit HO = 1)
V
OH
V
OL
I
o(sink)
I
o(source)
t
W
HIGH-level output voltage
LOW-level output voltage
output sink current
output source current
pulse width
I
o(source)
= 2 mA
I
o(sink)
= 2 mA
4.0
2
2
4.6
5.0
0.2
4.7
5.5
0.4
4.8
V
V
mA
mA
μ
s
at nominal horizontal
frequency
note 30
t
d
delay between mid sync of input
and mid HA pulse
0.3
0.45
0.6
μ
s
Switched to CLP output (bit HO = 0)
t
W
pulse width
at nominal horizontal
frequency
bit HD = 1 or
bit MACP = 1;
bits YD3 to YD0 = 1011;
at nominal horizontal
frequency
note 30
3.5
3.6
3.7
μ
s
t
d1
delay between start of CLP
pulse to start of black set-up
5.2
5.3
5.4
μ
s
t
d2
delay between mid sync of input
and start CLP pulse
3.0
3.2
3.4
μ
s
Switched to CLP input (bit ECL = 1)
V
IL
V
IH
t
W(clamp)
LOW-level input voltage
HIGH-level input voltage
clamping pulse width
0
2.4
1.8
3.5
0.6
5.5
V
V
μ
s
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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