xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
T
D
A
8295
_C2_2
NX
P
B
.V
.20
09.
A
llr
ight
s
r
e
s
e
rv
ed
.
Prod
uct
dat
a
sh
eet
Re
v
.02
—
2
7
Nove
mber
20
09
55
of
8
3
NXP
Semiconductors
TDA8295
Dig
ita
lg
lob
al
s
tan
dard
low
IF
demo
dulat
or
for
a
n
alog
TV
an
d
F
M
radio
[1]
Don’t care if CVBS_EQ_CTRL = 0; see
Table 36.Example of
Table 68: If an attenuation of around 1 dB for video frequencies greater than 2 MHz is wanted, the following
Table 68.
CVBS_EQ_COEFx_LOW and CVBS_EQ_COEFx_HIGH (x = 0 to 5) register (address 57h to 62h) bit description
Address Register
Bit
Symbol
Access Value
Description
57h
CVBS_EQ_COEF0_LOW
7 to 0 CVBS_EQ_COEF0[7:0]
R/W
00h*
The overall video (CVBS) equalizer is a symmetric FIR filter with
11 taps. Due to the symmetry the group delay is constant (linear
phase). The transfer function is as follows, while the sampling rate is
13.5 MHz:
Please note that because of the symmetry h0 = h10, h1 = h9, h2 = h8,
h3 = h7 and h4 = h6. The mid coefficient h5 is only present once.
CVBS_EQ_COEFx (x = 0 to 5) are defining the coefficients, i.e.
CVBS_EQ_COEF0 = h0 = h10, CVBS_EQ_COEF1 = h1 = h9,
CVBS_EQ_COEF2 = h2 = h8, CVBS_EQ_COEF3 = h3 = h7,
CVBS_EQ_COEF4 = h4 = h6 CVBS_EQ_COEF5 = h5. Each of the
coefficients h0 to h5 has got 12-bit quantization. The coefficients are in
signed fixed-point format, the representation is in two’s complement.
There is one sign bit, one magnitude bit and 10 fractional bits. Each
fractional bit represents an inverse power of two, so that the highest
value for a coefficient is 20 + 21 + ... + 210 = 21
210 =
1.9990234375. The binary representation for this value is
01.11 1111 1111 (= 7FFh) and all bits except the sign bit are logic 1. As
two’s complement is chosen, the lowest value for a coefficient is
2,
which is 10.00 0000 0000 (= 800h) in the binary representation. So, for
the lowest possible value, only the sign bit is logic 1. The shown
default values for CVBS_EQ_COEFx (x = 0 to 5) implement a flat
equalizer response.
58h
CVBS_EQ_COEF0_HIGH 7 to 4 -
R/W
-
3 to 0 CVBS_EQ_COEF0[11:8] R/W
0h*
59h
CVBS_EQ_COEF1_LOW
7 to 0 CVBS_EQ_COEF1[7:0]
R/W
00h*
5Ah
CVBS_EQ_COEF1_HIGH 7 to 4 -
R/W
-
3 to 0 CVBS_EQ_COEF1[11:8] R/W
0h*
5Bh
CVBS_EQ_COEF2_LOW
7 to 0 CVBS_EQ_COEF2[7:0]
R/W
00h*
5Ch
CVBS_EQ_COEF2_HIGH 7 to 4 -
R/W
-
3 to 0 CVBS_EQ_COEF2[11:8] R/W
0h*
5Dh
CVBS_EQ_COEF3_LOW
7 to 0 CVBS_EQ_COEF3[7:0]
R/W
00h*
5Eh
CVBS_EQ_COEF3_HIGH 7 to 4 -
R/W
-
3 to 0 CVBS_EQ_COEF3[11:8] R/W
0h*
5Fh
CVBS_EQ_COEF4_LOW
7 to 0 CVBS_EQ_COEF4[7:0]
R/W
00h*
60h
CVBS_EQ_COEF4_HIGH 7 to 4 -
R/W
-
3 to 0 CVBS_EQ_COEF4[11:8] R/W
0h*
61h
CVBS_EQ_COEF5_LOW
7 to 0 CVBS_EQ_COEF5[7:0]
R/W
00h*
62h
CVBS_EQ_COEF5_HIGH 7 to 4 -
R/W
-
3 to 0 CVBS_EQ_COEF5[11:8] R/W
4h*
Hz
()
h
0
h
1
z
1
–
×
h
2
z
2
–
×
h
3
z
3
–
×
h
4
z
4
–
×
...
h
10
z
10
–
×
++
+++
+
=