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參數(shù)資料
| 型號： | TC1307 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | Four-Channel CMOS LDO with Select Mode, Shutdown and Independent Reset |
| 中文描述： | 四通道CMOS低壓降穩(wěn)壓器的選擇模式，關(guān)機和獨立復(fù)位 |
| 文件頁數(shù)： | 13/28頁 |
| 文件大?。?/td> | 553K |
| 代理商： | TC1307 |
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2002 Microchip Technology Inc.
DS21702A-page 13
TC1307
4.0
DEVICE OVERVIEW
The TC1307 integrates four high performance linear
Low Dropout Regulators and a microcontroller reset
function.
As shown in the block diagram (Figure 4-3) using
dashed lines, each LDO has an independent shut-
down, error amplifier, P-MOS pass transistor and feed-
back divider resistors. All four LDOs share a common
voltage reference. LDO output numbers one and two
share a tri-state select input while LDO numbers three
and four share a tri-state select input. The select input
is used to program the LDO output voltage.
Also shown in the block diagram is the microcontroller
reset monitor. The reset monitor voltage detect input is
independent of the LDO input or output voltages.
4.1
Low Dropout Out Linear Regulators
4.1.1
OUTPUT
The TC1307 integrates four low drop out linear regula-
tors. Each regulator has 150 mA output current capa-
bility. A minimum of 1 μF output capacitance is required
on each of the LDOs for circuit stability. The output
capacitor type can be ceramic, tantalum or aluminum.
The esr range required for the output capacitor is 0
to 2
. To improve the dynamic performance of the
LDO in cases where sudden input voltage changes or
load current changes are present, larger capacitors can
be used.
The output voltage of the LDO can be selected using
the SELECT input pins. Table 4-1 summarizes how to
select the desired LDO output voltage for V
OUT1
and
V
OUT2
. Table 4-2 summarizes how to select the desired
LDO output voltage for V
OUT3
and V
OUT4
.
TABLE 4-1:
SELECT12 MODE settings.
TABLE 4-2:
SELECT34 MODE Settings.
4.1.2
INPUT
The TC1307, like all low drop out linear regulators,
requires a relatively low source impedance (< 10
)
tied to the V
IN
pin of the device to ensure circuit stabil-
ity. For battery applications or in applications that have
long lead length from the input voltage source to the
LDO V
IN
pin, a minimum capacitance of 2.2 μF is rec-
ommended to lower the source impedance. For appli-
cations that have more than 1 μF of capacitance on the
LDO outputs, higher input capacitance (4.7 μF) may be
needed to ensure stability.
4.1.3
SHUTDOWN OPERATION
Each LDO output can be enabled and disabled using
its respective shutdown input pin. For example, when
the level on SHDN1 is below the logic low level thresh-
old (V
IL
), LDO#1 output is disabled (P-Channel MOS-
FET is turned OFF). If all four shutdown inputs are
below V
IL
, the bandgap reference is turned off and the
shutdown current is typically less than 0.1 μA. The LDO
output will typically wake-up in 10 μs and the output will
settle in approximately 40 μs when brought out of shut-
down mode. See Figure 4-1 for timing definition. The
microcontroller RESET output function is independent
of all SHDN input pins.
4.2
Voltage Reset Monitor
The independent voltage reset output of the TC1307
can be used for low battery input voltage detect or
microcontroller power on reset function. The voltage
reset function monitors the voltage on the V
DET
pin.
The active low RESET output is capable of sourcing
and sinking current (Push-Pull). When the voltage on
the V
DET
pin is below the 2.63V typical threshold, the
RESET output pin is active low and capable of sinking
3.2 mA while holding the RESET output voltage below
0.4V. When the voltage on the V
DET
pin rises above the
2.63V typical threshold, the RESET output will remain
low for the T
RESET
time period. After the RESET time
out period, the RESET output voltage will transition to
the high output state (> V
DET
-1.5V when sourcing
800 μA), if the V
DET
pin remains above the threshold
voltage. The RESET output is current limited. The max-
imum source or sink current recommended for normal
operation is 10 mA.
The RESET output will be driven low within 100 μsec of
V
DET
pin going below the RESET voltage threshold of
2.63V typical. The RESET output will remain valid for
V
DET
voltages greater than 1.0V. See Figure 4-2 for
V
DET
and RESET output timing diagram.
SELECT12
V
OUT1
2.50V
2.80V
3.00V
V
OUT2
2.50V
2.80V
3.00V
GND
No Connect
V
IN
SELECT34
V
OUT3
1.80V
2.50V
2.80V
V
OUT4
1.80V
2.50V
2.80V
GND
No Connect
V
IN
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