參數(shù)資料
型號(hào): TAS5001PFBG4
廠(chǎng)商: Texas Instruments, Inc.
英文描述: TRUE DIGITAL AUDIO AMPLIFIER DIGITAL AUDIO PWM PROCESSOR
中文描述: 真正的數(shù)字音頻放大器,數(shù)字音頻PWM處理器
文件頁(yè)數(shù): 9/19頁(yè)
文件大?。?/td> 254K
代理商: TAS5001PFBG4
TAS5001
SLES009A
SEPTEMBER 2001
REVISED DECEMBER 2001
9
www.ti.com
functional description (continued)
de-emphasis selection
De-emphasis selection is accomplished by using the DEM_SEL and DEM_EN pins. See Table 3 for
de-emphasis selection description.
Table 3. De-Emphasis Selection
DEM_SEL
DEM_EN
DESCRIPTION
0
0
De-emphasis disabled
0
1
De-emphasis enabled for Fs = 44.1 kHz
1
1
De-emphasis enabled for Fs = 48 kHz
1
0
Forbidden mode. Do not use.
error status reporting (VALID_L and VALID_R)
The following is a list of the error conditions that will cause the VALID_L and VALID_R pins to be asserted low:
No clocks
Clock phase errors
When either of the above conditions is met, the VALID_L and VALID_R goes low and the PWM outputs go to
the hard mute state. If the error condition is removed, the TAS5001 is reinitialized and the VALID_L and VALID_R
pins are asserted high.
serial interface formats
The TAS5001 is compatible with eight different serial interfaces. Available interface options are IIS, right
justified, left justified, and DSP frame. Table 4 indicates how these options are selected using the MOD0, MOD1,
and MOD2 pins.
Table 4. Hardware Selection of Serial Audio Modes
MODE
MOD2 PIN
MOD1 PIN
MOD0 PIN
SERIAL INTERFACE
SDIN
0
1
2
3
4
5
6
7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
16 bit, MSB first; right justified
20 bit, MSB first; right justified
24 bit, MSB first; right justified
16 bit IIS
20 bit IIS
24 bit IIS
16 bit MSB first, left justified
16 bit DSP frame
The following figures illustrate the relationship between the SCLK, LRCLK and the serial data I/O for the different
interface protocols. Note that there are always 64 SCLKs per LRCLK. The nondata bits are padded with
binary 0s.
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