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參數(shù)資料
| 型號： | TAS5001PFBG4 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | TRUE DIGITAL AUDIO AMPLIFIER DIGITAL AUDIO PWM PROCESSOR |
| 中文描述： | 真正的數(shù)字音頻放大器，數(shù)字音頻PWM處理器 |
| 文件頁數(shù)： | 7/19頁 |
| 文件大?。?/td> | 254K |
| 代理商： | TAS5001PFBG4 |
TAS5001
SLES009A
–
SEPTEMBER 2001
–
REVISED DECEMBER 2001
7
www.ti.com
functional description (continued)
reset
The reset signal for the TAS5001 must be applied whenever toggling the M_S, DBSPD signal. This reset is
asynchronous. See Figure 3 for reset timing. To initiate the reset sequence the RESET pin is asserted low. As
long as the pin is held low the chip is in the reset state. During this reset time the PWM outputs are hard-muted
(P-outputs held low and M-outputs held high) and the PWM outputs valid pins (VALID_L. VALID_R) are held
low. Assuming PDN is high, the rising edge of the reset pulse begins chip initialization. After the initialization
time, the TAS5001 begins normal operation.
Initialization
Normal
Operation
RESET
PDN
Normal Operation
5 ms max
VALID_L
VALID_R
Figure 3. Reset Timing
power down
When PDN is low (see Figure 4), both the PLL and the oscillator are shut down. Note that power down is an
asynchronous operation. To place the device in total power-down mode, both RESET and PDN must be held
low. As long as these pins are held low, the chip is in the power-down state and the PWM outputs are hard muted
with the P outputs held low and the M outputs held high. To place the device back into normal mode, see the
power up
section.
NOTE:
In order for the dynamic logic to be properly powered down, the clocks should not be stopped
before the PDN pin goes low. Otherwise, the device may drain additional supply current.
Initialization
Chip
Power-Down
PDN and RESET
Normal Operation
Normal
Operation
VALID
Figure 4. Power-Down Timing
mute
The TAS5001 provides a mute function that is used when the MUTE pin is asserted low. See Table 2 for mute
description. This mute is a quiet mute; that is, the mute is accomplished by outputting a zero value waveform
in which both sides of the differential PWM outputs have a 50% duty cycle (see Figure 5 for mute timing).
Table 2. Mute Description
MUTE
PWM_P
PWM_M
DESCRIPTION
0
50% duty cycle
50% duty cycle
Mute
1
DATA
DATA
Normal operation
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| TAS5001PFBR | 功能描述:音頻 DSP Digital Audio PWM Processor RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| TAS5001PFBRG4 | 功能描述:音頻 DSP Dig Aud PWM Proc RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| TAS5010 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:TRUE DIGITAL AUDIO AMPLIFIER TAS5010 DIGITAL AUDIO PWM PROCESSOR |
| TAS5010_06 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:TRUE DIGITAL AUDIO AMPLIFIER DIGITAL AUDIO PWM PROCESSOR |
| TAS5010-5112F2EVM | 功能描述:音頻 IC 開發(fā)工具 TAS5010-5112F2 Eval Mod RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V |
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